https://gcc.gnu.org/g:0964a8f15e9b129522940ab0911b7d3fa4754f98
commit r15-978-g0964a8f15e9b129522940ab0911b7d3fa4754f98
Author: Lingling Kong <lingling.k...@intel.com>
Date: Mon Jun 3 11:10:36 2024 +0800
[APX NF] Support APX NF for right shift insns
gcc/ChangeLog:
* config/i386/i386.md (*ashr<mode>3_1<nf_name>): New
define_insn.
(*lshr<mode>3_1<nf_name>): Ditto.
(*lshrqi3_1<nf_name>): Ditto.
(*lshrhi3_1<nf_name>): Ditto.
Diff:
---
gcc/config/i386/i386.md | 82 +++++++++++++++++++++++++++----------------------
1 file changed, 46 insertions(+), 36 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8063cb576f5..f1c828a6dc3 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -16325,13 +16325,13 @@
[(set_attr "type" "ishiftx")
(set_attr "mode" "<MODE>")])
-(define_insn "*ashr<mode>3_1"
+(define_insn "*ashr<mode>3_1<nf_name>"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r")
(ashiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm,rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>,r,c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,r,c<S>")))]
+ "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16342,11 +16342,11 @@
default:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "sar{<imodesuffix>}\t%0";
else
- return use_ndd ? "sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>sar{<imodesuffix>}\t{%2, %1, %0|%0, %1,
%2}"
+ : "<nf_prefix>sar{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set_attr "isa" "*,bmi2,apx_ndd")
@@ -16386,14 +16386,13 @@
}
[(set_attr "isa" "*,*,*,apx_ndd")])
-
-(define_insn "*lshr<mode>3_1"
+(define_insn "*lshr<mode>3_1<nf_name>"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,?k,r")
(lshiftrt:SWI48
(match_operand:SWI48 1 "nonimmediate_operand" "0,rm,k,rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>,r,<KS>,c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "c<S>,r,<KS>,c<S>")))]
+ "ix86_binary_operator_ok (LSHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16405,11 +16404,11 @@
default:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "shr{<imodesuffix>}\t%0";
else
- return use_ndd ? "shr{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "shr{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>shr{<imodesuffix>}\t{%2, %1, %0|%0, %1,
%2}"
+ : "<nf_prefix>shr{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set_attr "isa" "*,bmi2,avx512bw,apx_ndd")
@@ -16425,6 +16424,17 @@
(set_attr "mode" "<MODE>")])
;; Convert shift to the shiftx pattern to avoid flags dependency.
+;; For NF/NDD doesn't support shift count as r, it just support c<S>,
+;; and it has no flag.
+(define_split
+ [(set (match_operand:SWI48 0 "register_operand")
+ (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand")))]
+ "TARGET_BMI2 && reload_completed"
+ [(set (match_dup 0)
+ (any_shiftrt:SWI48 (match_dup 1) (match_dup 2)))]
+ "operands[2] = gen_lowpart (<MODE>mode, operands[2]);")
+
(define_split
[(set (match_operand:SWI48 0 "register_operand")
(any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
@@ -16493,22 +16503,22 @@
(zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
"operands[2] = gen_lowpart (SImode, operands[2]);")
-(define_insn "*ashr<mode>3_1"
+(define_insn "*ashr<mode>3_1<nf_name>"
[(set (match_operand:SWI12 0 "nonimmediate_operand" "=<r>m, r")
(ashiftrt:SWI12
(match_operand:SWI12 1 "nonimmediate_operand" "0, rm")
- (match_operand:QI 2 "nonmemory_operand" "c<S>, c<S>")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "c<S>, c<S>")))]
+ "ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "sar{<imodesuffix>}\t%0";
else
- return use_ndd ? "sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
- : "sar{<imodesuffix>}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>sar{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>sar{<imodesuffix>}\t{%2, %0|%0, %2}";
}
[(set_attr "isa" "*, apx_ndd")
(set_attr "type" "ishift")
@@ -16521,13 +16531,13 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*lshrqi3_1"
+(define_insn "*lshrqi3_1<nf_name>"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?k,r")
(lshiftrt:QI
(match_operand:QI 1 "nonimmediate_operand" "0, k, rm")
- (match_operand:QI 2 "nonmemory_operand" "cI,Wb,cI")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (LSHIFTRT, QImode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "cI,Wb,cI")))]
+ "ix86_binary_operator_ok (LSHIFTRT, QImode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16535,11 +16545,11 @@
case TYPE_ISHIFT:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "shr{b}\t%0";
else
- return use_ndd ? "shr{b}\t{%2, %1, %0|%0, %1, %2}"
- : "shr{b}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>shr{b}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>shr{b}\t{%2, %0|%0, %2}";
case TYPE_MSKLOG:
return "#";
default:
@@ -16558,13 +16568,13 @@
(const_string "*")))
(set_attr "mode" "QI")])
-(define_insn "*lshrhi3_1"
+(define_insn "*lshrhi3_1<nf_name>"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm, ?k, r")
(lshiftrt:HI
(match_operand:HI 1 "nonimmediate_operand" "0, k, rm")
- (match_operand:QI 2 "nonmemory_operand" "cI, Ww, cI")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (LSHIFTRT, HImode, operands, TARGET_APX_NDD)"
+ (match_operand:QI 2 "nonmemory_operand" "cI, Ww, cI")))]
+ "ix86_binary_operator_ok (LSHIFTRT, HImode, operands, TARGET_APX_NDD)
+ && <nf_condition>"
{
bool use_ndd = get_attr_isa (insn) == ISA_APX_NDD;
switch (get_attr_type (insn))
@@ -16572,11 +16582,11 @@
case TYPE_ISHIFT:
if (operands[2] == const1_rtx
&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && !use_ndd)
+ && !use_ndd && !<nf_applied>)
return "shr{w}\t%0";
else
- return use_ndd ? "shr{w}\t{%2, %1, %0|%0, %1, %2}"
- : "shr{w}\t{%2, %0|%0, %2}";
+ return use_ndd ? "<nf_prefix>shr{w}\t{%2, %1, %0|%0, %1, %2}"
+ : "<nf_prefix>shr{w}\t{%2, %0|%0, %2}";
case TYPE_MSKLOG:
return "#";
default:
