https://gcc.gnu.org/g:28ac63180e000843ba4a82384407bcc203f27853
commit r15-981-g28ac63180e000843ba4a82384407bcc203f27853
Author: Lingling Kong <lingling.k...@intel.com>
Date: Mon Jun 3 14:22:07 2024 +0800
[APX NF] Support APX NF for mul/div
gcc/ChangeLog:
* config/i386/i386.md (*mul<mode>3_1<nf_name>): New define_insn.
(*mulqi3_1<nf_name>): Ditto.
(*<u>divmod<mode>4_noext_nf): Ditto.
(<u>divmodhiqi3<nf_name>): Ditto.
Diff:
---
gcc/config/i386/i386.md | 47 ++++++++++++++++++++++++++++++-----------------
1 file changed, 30 insertions(+), 17 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b4233ab99fe..48ca19cb8df 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -9900,17 +9900,17 @@
;;
;; On BDVER1, all HI MULs use DoublePath
-(define_insn "*mul<mode>3_1"
+(define_insn "*mul<mode>3_1<nf_name>"
[(set (match_operand:SWIM248 0 "register_operand" "=r,r,r")
(mult:SWIM248
(match_operand:SWIM248 1 "nonimmediate_operand" "%rm,rm,0")
- (match_operand:SWIM248 2 "<general_operand>" "K,<i>,<m>r")))
- (clobber (reg:CC FLAGS_REG))]
- "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
+ (match_operand:SWIM248 2 "<general_operand>" "K,<i>,<m>r")))]
+ "!(MEM_P (operands[1]) && MEM_P (operands[2]))
+ && <nf_condition>"
"@
- imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
- imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
- imul{<imodesuffix>}\t{%2, %0|%0, %2}"
+ <nf_prefix>imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ <nf_prefix>imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ <nf_prefix>imul{<imodesuffix>}\t{%2, %0|%0, %2}"
[(set_attr "type" "imul")
(set_attr "prefix_0f" "0,0,1")
(set (attr "athlon_decode")
@@ -9971,14 +9971,14 @@
;; MUL reg8 Direct
;; MUL mem8 Direct
-(define_insn "*mulqi3_1"
+(define_insn "*mulqi3_1<nf_name>"
[(set (match_operand:QI 0 "register_operand" "=a")
(mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "nonimmediate_operand" "qm")))
- (clobber (reg:CC FLAGS_REG))]
+ (match_operand:QI 2 "nonimmediate_operand" "qm")))]
"TARGET_QIMODE_MATH
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
- "mul{b}\t%2"
+ && !(MEM_P (operands[1]) && MEM_P (operands[2]))
+ && <nf_condition>"
+ "<nf_prefix>mul{b}\t%2"
[(set_attr "type" "imul")
(set_attr "length_immediate" "0")
(set (attr "athlon_decode")
@@ -11121,6 +11121,19 @@
[(set_attr "type" "multi")
(set_attr "mode" "SI")])
+(define_insn "*<u>divmod<mode>4_noext_nf"
+ [(set (match_operand:SWIM248 0 "register_operand" "=a")
+ (any_div:SWIM248
+ (match_operand:SWIM248 2 "register_operand" "0")
+ (match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
+ (set (match_operand:SWIM248 1 "register_operand" "=d")
+ (<paired_mod>:SWIM248 (match_dup 2) (match_dup 3)))
+ (use (match_operand:SWIM248 4 "register_operand" "1"))]
+ "TARGET_APX_NF"
+ "%{nf%} <sgnprefix>div{<imodesuffix>}\t%3"
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "<MODE>")])
+
(define_insn "*<u>divmod<mode>4_noext"
[(set (match_operand:SWIM248 0 "register_operand" "=a")
(any_div:SWIM248
@@ -11268,7 +11281,7 @@
;; Change div/mod to HImode and extend the second argument to HImode
;; so that mode of div/mod matches with mode of arguments. Otherwise
;; combine may fail.
-(define_insn "<u>divmodhiqi3"
+(define_insn "<u>divmodhiqi3<nf_name>"
[(set (match_operand:HI 0 "register_operand" "=a")
(ior:HI
(ashift:HI
@@ -11280,10 +11293,10 @@
(const_int 8))
(zero_extend:HI
(truncate:QI
- (div:HI (match_dup 1) (any_extend:HI (match_dup 2)))))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_QIMODE_MATH"
- "<sgnprefix>div{b}\t%2"
+ (div:HI (match_dup 1) (any_extend:HI (match_dup 2)))))))]
+ "TARGET_QIMODE_MATH
+ && <nf_condition>"
+ "<nf_prefix><sgnprefix>div{b}\t%2"
[(set_attr "type" "idiv")
(set_attr "mode" "QI")])
