https://gcc.gnu.org/g:46132ad0081e4f55c19977b00f4c6d9280cead21
commit 46132ad0081e4f55c19977b00f4c6d9280cead21
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Mon Jun 10 18:00:27 2024 -0400
Add options for modes in SPR registers.
2024-06-10 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -m{cc,qi,hi,si,sf,df}spr.
(rs6000_debug_reg_global): Print out SPR mode options.
* config/rs6000/rs6000.opt (-mccspr): New option.
(-mqispr): Likewise.
(-mhispr): Likewise.
(-msispr): Likewise.
(-msfspr): Likewise.
(-mdfspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 60 ++++++++++++++++++++++++++++++++++++++------
gcc/config/rs6000/rs6000.opt | 24 ++++++++++++++++++
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c106e13b8ad..70214e4b28c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1946,18 +1946,44 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
{
case VRSAVE_REGNO:
case VSCR_REGNO:
+ return (!orig_complex_p && mode == SImode);
+
case LR_REGNO:
+ return (!orig_complex_p && mode == Pmode);
+
case CTR_REGNO:
case TAR_REGNO:
- {
- unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
- ? 4
- : UNITS_PER_WORD);
+ if (orig_complex_p)
+ return 0;
- return (!orig_complex_p
- && GET_MODE_SIZE (mode) <= reg_size
- && SCALAR_INT_MODE_P (mode));
- }
+ if (GET_MODE_CLASS (mode) == MODE_CC)
+ return TARGET_CCSPR != 0;
+
+ switch (mode)
+ {
+ case E_QImode:
+ return TARGET_QISPR != 0;
+
+ case E_HImode:
+ return TARGET_HISPR != 0;
+
+ case E_SImode:
+ return (TARGET_SISPR != 0 || !TARGET_POWERPC64);
+
+ case E_DImode:
+ return TARGET_POWERPC64;
+
+ case E_SFmode:
+ return (TARGET_SFSPR != 0);
+
+ case E_DFmode:
+ return (TARGET_DFSPR != 0 && TARGET_POWERPC64);
+
+ default:
+ break;
+ }
+
+ return false;
default:
break;
@@ -2621,6 +2647,24 @@ rs6000_debug_reg_global (void)
if (TARGET_DIRECT_MOVE_128)
fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
(int)VECTOR_ELEMENT_MFVSRLD_64BIT);
+
+ if (TARGET_CCSPR)
+ fprintf (stderr, DEBUG_FMT_S, "Condition modes in SPR", "yes");
+
+ if (TARGET_QISPR)
+ fprintf (stderr, DEBUG_FMT_S, "QImode in SPR", "yes");
+
+ if (TARGET_HISPR)
+ fprintf (stderr, DEBUG_FMT_S, "HImode in SPR", "yes");
+
+ if (TARGET_SISPR)
+ fprintf (stderr, DEBUG_FMT_S, "SImode in SPR", "yes");
+
+ if (TARGET_SFSPR)
+ fprintf (stderr, DEBUG_FMT_S, "SFmode in SPR", "yes");
+
+ if (TARGET_DFSPR)
+ fprintf (stderr, DEBUG_FMT_S, "DFmode in SPR", "yes");
}
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 7f7a283bc99..27f873972b5 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -634,6 +634,30 @@ mtar
Target Undocumented Mask(TAR) Var(rs6000_isa_flags)
Allow (do not allow) use the TAR register.
+mccspr
+Target Undocumented Var(TARGET_CCSPR) Init(0)
+Allow (do not allow) condition modes to be in the CTR or TAR registers.
+
+mqispr
+Target Undocumented Var(TARGET_QISPR) Init(1)
+Allow (do not allow) 8-bit integers to be in the CTR or TAR registers.
+
+mhispr
+Target Undocumented Var(TARGET_HISPR) Init(1)
+Allow (do not allow) 16-bit integers to be in the CTR or TAR registers.
+
+msispr
+Target Undocumented Var(TARGET_SISPR) Init(1)
+Allow (do not allow) 32-bit integers to be in the CTR or TAR registers.
+
+msfspr
+Target Undocumented Var(TARGET_SFSPR) Init(0)
+Allow (do not allow) 32-bit floating point to be in the CTR or TAR registers.
+
+mdfspr
+Target Undocumented Var(TARGET_DFSPR) Init(0)
+Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
