https://gcc.gnu.org/g:1232a584429302448e9ff8dee30e92901b37870a
commit 1232a584429302448e9ff8dee30e92901b37870a
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Jun 11 18:23:32 2024 -0400
Add -mlrspr.
2024-06-11 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -mlrspr.
* config/rs6000/rs6000.opt (-mlrspr): New debug option.
Diff:
---
gcc/config/rs6000/rs6000.cc | 4 +++-
gcc/config/rs6000/rs6000.opt | 4 ++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 70214e4b28c5..3e118c866081 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1949,7 +1949,9 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
return (!orig_complex_p && mode == SImode);
case LR_REGNO:
- return (!orig_complex_p && mode == Pmode);
+ if (!TARGET_LRSPR)
+ return (!orig_complex_p && mode == Pmode);
+ /* fall through. */
case CTR_REGNO:
case TAR_REGNO:
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 27f873972b57..137290b8364f 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -658,6 +658,10 @@ mdfspr
Target Undocumented Var(TARGET_DFSPR) Init(0)
Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers.
+mlrspr
+Target Undocumented Var(TARGET_LRSPR) Init(0)
+Treat (do not treat) the LR register like CTR/TAR in terms of what modes it
can hold.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
