https://gcc.gnu.org/g:15815b4bba3cd54427f8e9ef3f1432eaa2b1ff82
commit 15815b4bba3cd54427f8e9ef3f1432eaa2b1ff82
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Jun 13 13:48:27 2024 -0400
Revert changes
Diff:
---
gcc/config/rs6000/rs6000.cc | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 02be24b1a914..c5c4191127e4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,13 +1851,9 @@ static int
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
- bool orig_complex_p = false;
if (COMPLEX_MODE_P (mode))
- {
- mode = GET_MODE_INNER (mode);
- orig_complex_p = true;
- }
+ mode = GET_MODE_INNER (mode);
/* Vector pair modes need even/odd VSX register pairs. Only allow vector
registers. */
@@ -1939,18 +1935,6 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CA_REGNO_P (regno))
return mode == Pmode || mode == SImode;
- /* Do some consistancy checks for SPRs. Don't allow complex modes.
- VRSAVE/VSCR are always 32-bit SPRs. Don't allow floating point modes in
- the other SPRs. Don't allow large modes that don't fit in a single
- register. */
- if (regno == VRSAVE_REGNO || regno == VSCR_REGNO)
- return (!orig_complex_p && mode == SImode);
-
- if (regno == LR_REGNO || regno == CTR_REGNO)
- return (!orig_complex_p
- && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
- && !SCALAR_FLOAT_MODE_P (mode));
-
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
