https://gcc.gnu.org/g:8fc24dd1cf8d0462e20373fe587ee3cad0b84234
commit 8fc24dd1cf8d0462e20373fe587ee3cad0b84234
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Jun 13 14:51:34 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.test | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 4c1c466a3db6..a6f3be611739 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,13 +1,33 @@
==================== Branch work168-test, patch #300 ====================
+Possibly restrict SPRs from holding small integers or CCs.
+
+2024-06-13 Michael Meissner <meiss...@linux.ibm.com>
+
+ * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
+ support for -mccspr and -mintspr which controls whether SPRs can hold
+ condition code modes or small integers.
+ (rs6000_debug_reg_global): Print out -mccspr and -mintspr options.
+ * config/rs6000/rs6000.opt (-mccspr): New option.
+ (-mintspr): Likewise.
+
+==================== Branch work168-test, patch #300 ====================
+
Restrict modes that can got in SPRs.
-2024-06-04 Michael Meissner <meiss...@linux.ibm.com>
+2024-06-13 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict
the modes that can go in SPR registers.
+ * config/rs6000/rs6000.md (movsf_hardfloat): Eliminate alternatives for
+ moving floating point to/from SPRs.
+ (movsd_hardfloat): Likewise.
+ (mov<mode>_softfloat): Likewise.
+ (mov<mode>_softfloat32): Likewise.
+ (mov<mode>_hardfloat64): Likewise.
+ (mov<mode>_softfloat64): Likewise.
==================== Branch work168-test, patch #11 from work168 branch
====================
