[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vwsll combine on rv32 targets

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:23840c32e5f3bae1f23dc25a10567e50b31b73db

commit 23840c32e5f3bae1f23dc25a10567e50b31b73db
Author: Edwin Lu <e...@rivosinc.com>
Date:   Tue Jun 11 13:50:02 2024 -0700

    RISC-V: Fix vwsll combine on rv32 targets
    
    On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in
    maybe_legitimize_instruction when zero extending a uint32 to uint64 due
    to a mismatch between the input operand's mode (DI) and the expanded insn
    operand's mode (Pmode == SI). Ensure that mode of the operands match
    
    gcc/ChangeLog:
    
            * config/riscv/autovec-opt.md: Fix mode mismatch
    
    Signed-off-by: Edwin Lu <e...@rivosinc.com>
    Co-authored-by: Robin Dapp <rd...@ventanamicro.com>
    (cherry picked from commit 6638ba17eadc0f450faa3d8c2f77afe7fdb20614)

Diff:
---
 gcc/config/riscv/autovec-opt.md | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 6a2eabbd854..d7a3cfd4602 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1517,8 +1517,7 @@
   "&& 1"
   [(const_int 0)]
   {
-    if (GET_CODE (operands[2]) == SUBREG)
-      operands[2] = SUBREG_REG (operands[2]);
+    operands[2] = gen_lowpart (Pmode, operands[2]);
     insn_code icode = code_for_pred_vwsll_scalar (<MODE>mode);
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
     DONE;
@@ -1584,8 +1583,7 @@
   "&& 1"
   [(const_int 0)]
   {
-    if (GET_CODE (operands[2]) == SUBREG)
-      operands[2] = SUBREG_REG (operands[2]);
+    operands[2] = gen_lowpart (Pmode, operands[2]);
     insn_code icode = code_for_pred_vwsll_scalar (<V_DOUBLE_TRUNC>mode);
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
     DONE;