https://gcc.gnu.org/g:b7a16ad1df8b00e084ef6bf0c23e5f8bdc5f419b

commit r14-10408-gb7a16ad1df8b00e084ef6bf0c23e5f8bdc5f419b
Author: Andre Vieira <andre.simoesdiasvie...@arm.com>
Date:   Thu Jul 11 15:38:45 2024 +0100

    mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]
    
    This patch fixes the backend pattern that was printing the wrong input
    scalar register pair when inserting into lane 1.
    
    Added a new test to force float-abi=hard so we can use scan-assembler to 
check
    correct codegen.
    
    gcc/ChangeLog:
    
            PR target/115611
            * config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of 
input
            scalar register pair when lane = 1.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.
    
    (cherry picked from commit 7c11fdd2cc11a7058e9643b6abf27831970ad2c9)

Diff:
---
 gcc/config/arm/mve.md                              |  2 +-
 .../arm/mve/intrinsics/vsetq_lane_su64.c           | 63 ++++++++++++++++++++++
 2 files changed, 64 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 9fe51298cdc2..f45c555ef063 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -6505,7 +6505,7 @@
   if (elt == 0)
    return "vmov\t%e0, %Q1, %R1";
   else
-   return "vmov\t%f0, %J1, %K1";
+   return "vmov\t%f0, %Q1, %R1";
 }
  [(set_attr "type" "mve_move")])
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c 
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
new file mode 100644
index 000000000000..5aa3bc9a76a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c
@@ -0,0 +1,63 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-additional-options "-mfloat-abi=hard -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "arm_mve.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**fn1:
+**     vmov    d0, r0, r1
+**     bx      lr
+*/
+uint64x2_t
+fn1 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 0);
+}
+
+/*
+**fn2:
+**     vmov    d1, r0, r1
+**     bx      lr
+*/
+uint64x2_t
+fn2 (uint64_t a, uint64x2_t b)
+{
+  return vsetq_lane_u64 (a, b, 1);
+}
+
+/*
+**fn3:
+**     vmov    d0, r0, r1
+**     bx      lr
+*/
+int64x2_t
+fn3 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 0);
+}
+
+/*
+**fn4:
+**     vmov    d1, r0, r1
+**     bx      lr
+*/
+int64x2_t
+fn4 (int64_t a, int64x2_t b)
+{
+  return vsetq_lane_s64 (a, b, 1);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
+

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