https://gcc.gnu.org/g:ecc2c3cb7235f2d3a75cb3909cace7f6a38a4062
commit r15-2089-gecc2c3cb7235f2d3a75cb3909cace7f6a38a4062
Author: Haochen Gui <guih...@gcc.gnu.org>
Date: Wed Jul 17 14:47:36 2024 +0800
rs6000: Remove redundant guard for float128 mode pattern
gcc/
* config/rs6000/rs6000.md (mov<mode>cc, *mov<mode>cc_p10,
*mov<mode>cc_invert_p10, *fpmask<mode>, *xxsel<mode>,
@ieee_128bit_vsx_abs<mode>2, *ieee_128bit_vsx_nabs<mode>2,
add<mode>3, sub<mode>3, mul<mode>3, div<mode>3, sqrt<mode>2,
copysign<mode>3, copysign<mode>3_hard, copysign<mode>3_soft,
@neg<mode>2_hw, @abs<mode>2_hw, *nabs<mode>2_hw, fma<mode>4_hw,
*fms<mode>4_hw, *nfma<mode>4_hw, *nfms<mode>4_hw,
extend<SFDF:mode><IEEE128:mode>2_hw, trunc<mode>df2_hw,
trunc<mode>sf2_hw, fix<uns>_<IEEE128:mode><SDI:mode>2_hw,
fix<uns>_trunc<IEEE128:mode><QHI:mode>2,
*fix<uns>_trunc<IEEE128:mode><QHSI:mode>2_mem,
float_<mode>di2_hw, float_<mode>si2_hw,
float<QHI:mode><IEEE128:mode>2, floatuns_<mode>di2_hw,
floatuns_<mode>si2_hw, floatuns<QHI:mode><IEEE128:mode>2,
floor<mode>2, ceil<mode>2, btrunc<mode>2, round<mode>2,
add<mode>3_odd, sub<mode>3_odd, mul<mode>3_odd, div<mode>3_odd,
sqrt<mode>2_odd, fma<mode>4_odd, *fms<mode>4_odd, *nfma<mode>4_odd,
*nfms<mode>4_odd, trunc<mode>df2_odd, *cmp<mode>_hw for IEEE128):
Remove guard FLOAT128_IEEE_P.
(@extenddf<mode>2_fprs, @extenddf<mode>2_vsx,
trunc<mode>df2_internal1, trunc<mode>df2_internal2,
fix_trunc_helper<mode>, neg<mode>2, *cmp<mode>_internal1,
*cmp<IBM128:mode>_internal2 for IBM128): Remove guard
FLOAT128_IBM_P.
Diff:
---
gcc/config/rs6000/rs6000.md | 115 ++++++++++++++++++++++----------------------
1 file changed, 57 insertions(+), 58 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6a2891c5e509..f59be5365708 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5701,7 +5701,7 @@
(if_then_else:IEEE128 (match_operand 1 "comparison_operator")
(match_operand:IEEE128 2 "gpc_reg_operand")
(match_operand:IEEE128 3 "gpc_reg_operand")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
@@ -5718,7 +5718,7 @@
(match_operand:IEEE128 4 "altivec_register_operand" "v,v")
(match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
(clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 6)
@@ -5750,7 +5750,7 @@
(match_operand:IEEE128 4 "altivec_register_operand" "v,v")
(match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
(clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 6)
@@ -5785,7 +5785,7 @@
(match_operand:IEEE128 3 "altivec_register_operand" "v")])
(match_operand:V2DI 4 "all_ones_constant" "")
(match_operand:V2DI 5 "zero_constant" "")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"xscmp%V1qp %0,%2,%3"
[(set_attr "type" "fpcompare")])
@@ -5796,7 +5796,7 @@
(match_operand:V2DI 2 "zero_constant" ""))
(match_operand:IEEE128 3 "altivec_register_operand" "v")
(match_operand:IEEE128 4 "altivec_register_operand" "v")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"xxsel %x0,%x4,%x3,%x1"
[(set_attr "type" "vecmove")])
@@ -8869,7 +8869,7 @@
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
(use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
"!TARGET_VSX && TARGET_HARD_FLOAT
- && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
+ && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 3) (match_dup 1))
@@ -8886,7 +8886,7 @@
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d")
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "wa,m")))]
- "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
+ "TARGET_LONG_DOUBLE_128 && TARGET_VSX"
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
@@ -8932,7 +8932,7 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
(float_truncate:DF
(match_operand:IBM128 1 "gpc_reg_operand" "0,d")))]
- "FLOAT128_IBM_P (<MODE>mode) && !TARGET_XL_COMPAT
+ "!TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"@
#
@@ -8948,7 +8948,7 @@
(define_insn "trunc<mode>df2_internal2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
- "FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT
+ "TARGET_XL_COMPAT && TARGET_HARD_FLOAT
&& TARGET_LONG_DOUBLE_128"
"fadd %0,%1,%L1"
[(set_attr "type" "fp")])
@@ -9001,7 +9001,7 @@
(unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")]
UNSPEC_FIX_TRUNC_TF))
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
- "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
+ "TARGET_HARD_FLOAT"
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
[(set_attr "type" "fp")
(set_attr "length" "20")])
@@ -9156,7 +9156,7 @@
(define_insn "neg<mode>2_internal"
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d")
(neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
- "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
+ "TARGET_HARD_FLOAT"
{
if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
return "fneg %L0,%L1\;fneg %0,%1";
@@ -9278,7 +9278,7 @@
[(set (match_operand:IEEE128 0 "register_operand" "=wa")
(abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
(clobber (match_scratch:V16QI 2 "=v"))]
- "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW"
"#"
"&& 1"
[(parallel [(set (match_dup 0)
@@ -9308,8 +9308,7 @@
(abs:IEEE128
(match_operand:IEEE128 1 "register_operand" "wa"))))
(clobber (match_scratch:V16QI 2 "=v"))]
- "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW
- && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW"
"#"
"&& 1"
[(parallel [(set (match_dup 0)
@@ -12656,7 +12655,7 @@
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d")
(match_operand:IBM128 2 "gpc_reg_operand" "d")))]
- "!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
+ "!TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
[(set_attr "type" "fpcompare")
@@ -12675,7 +12674,7 @@
(clobber (match_scratch:DF 9 "=d"))
(clobber (match_scratch:DF 10 "=d"))
(clobber (match_scratch:GPR 11 "=b"))]
- "TARGET_XL_COMPAT && FLOAT128_IBM_P (<IBM128:MODE>mode)
+ "TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
@@ -14972,7 +14971,7 @@
(plus:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsaddqp %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -14982,7 +14981,7 @@
(minus:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssubqp %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -14992,7 +14991,7 @@
(mult:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmulqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15002,7 +15001,7 @@
(div:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsdivqp %0,%1,%2"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15011,7 +15010,7 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(sqrt:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssqrtqp %0,%1"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15020,7 +15019,7 @@
[(use (match_operand:IEEE128 0 "altivec_register_operand"))
(use (match_operand:IEEE128 1 "altivec_register_operand"))
(use (match_operand:IEEE128 2 "any_operand"))]
- "FLOAT128_IEEE_P (<MODE>mode)"
+ ""
{
/* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
but PowerPC prefers -fabs (x). */
@@ -15054,7 +15053,7 @@
(copysign:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscpsgnqp %0,%2,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15065,7 +15064,7 @@
(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")))
(clobber (match_scratch:IEEE128 3 "=&v"))]
- "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "!TARGET_FLOAT128_HW"
"xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
[(set_attr "type" "veccomplex")
(set_attr "length" "8")])
@@ -15074,7 +15073,7 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnegqp %0,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15084,7 +15083,7 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(abs:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsabsqp %0,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15095,7 +15094,7 @@
(neg:IEEE128
(abs:IEEE128
(match_operand:IEEE128 1 "altivec_register_operand" "v"))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnabsqp %0,%1"
[(set_attr "type" "vecmove")
(set_attr "size" "128")])
@@ -15107,7 +15106,7 @@
(match_operand:IEEE128 1 "altivec_register_operand" "%v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmaddqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15119,7 +15118,7 @@
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmsubqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15131,7 +15130,7 @@
(match_operand:IEEE128 1 "altivec_register_operand" "%v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmaddqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15144,7 +15143,7 @@
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0")))))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmsubqp %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15153,7 +15152,7 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(float_extend:IEEE128
(match_operand:SFDF 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvdpqp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15196,7 +15195,7 @@
[(set (match_operand:DF 0 "altivec_register_operand" "=v")
(float_truncate:DF
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqpdp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15209,7 +15208,7 @@
(float_truncate:SF
(match_operand:IEEE128 1 "altivec_register_operand" "v")))
(clobber (match_scratch:DF 2 "=v"))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 2)
@@ -15239,7 +15238,7 @@
(define_insn "fix<uns>_<IEEE128:mode><SDI:mode>2_hw"
[(set (match_operand:SDI 0 "altivec_register_operand" "=v")
(any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqp<su><wd>z %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15248,7 +15247,7 @@
[(set (match_operand:QHI 0 "altivec_register_operand" "=v")
(any_fix:QHI
(match_operand:IEEE128 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqp<su>wz %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15260,7 +15259,7 @@
(any_fix:QHSI
(match_operand:IEEE128 1 "altivec_register_operand" "v")))
(clobber (match_scratch:QHSI 2 "=v"))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -15271,7 +15270,7 @@
(define_insn "float_<mode>di2_hw"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(float:IEEE128 (match_operand:DI 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvsdqp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15280,7 +15279,7 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "vrZ")))
(clobber (match_scratch:DI 2 "=v"))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 2)
@@ -15299,7 +15298,7 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v")
(float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z")))
(clobber (match_scratch:DI 2 "=X,r,X"))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -15336,7 +15335,7 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unsigned_float:IEEE128
(match_operand:DI 1 "altivec_register_operand" "v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvudqp %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15346,7 +15345,7 @@
(unsigned_float:IEEE128
(match_operand:SI 1 "nonimmediate_operand" "vrZ")))
(clobber (match_scratch:DI 2 "=v"))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 2)
@@ -15366,7 +15365,7 @@
(unsigned_float:IEEE128
(match_operand:QHI 1 "nonimmediate_operand" "v,r,Z")))
(clobber (match_scratch:DI 2 "=X,r,X"))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
+ "TARGET_FLOAT128_HW"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -15399,7 +15398,7 @@
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIM))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 1,%0,%1,3"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15409,7 +15408,7 @@
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIP))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 1,%0,%1,2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15419,7 +15418,7 @@
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIZ))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 1,%0,%1,1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15429,7 +15428,7 @@
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_FRIN))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsrqpi 0,%0,%1,0"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15441,7 +15440,7 @@
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_ADD_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsaddqpo %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15452,7 +15451,7 @@
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_SUB_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssubqpo %0,%1,%2"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15463,7 +15462,7 @@
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_MUL_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmulqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15474,7 +15473,7 @@
[(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_DIV_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsdivqpo %0,%1,%2"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15484,7 +15483,7 @@
(unspec:IEEE128
[(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_SQRT_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xssqrtqpo %0,%1"
[(set_attr "type" "vecdiv")
(set_attr "size" "128")])
@@ -15496,7 +15495,7 @@
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmaddqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15509,7 +15508,7 @@
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsmsubqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15522,7 +15521,7 @@
(match_operand:IEEE128 2 "altivec_register_operand" "v")
(match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD)))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmaddqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15536,7 +15535,7 @@
(neg:IEEE128
(match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD)))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xsnmsubqpo %0,%1,%2"
[(set_attr "type" "qmul")
(set_attr "size" "128")])
@@ -15545,7 +15544,7 @@
[(set (match_operand:DF 0 "vsx_register_operand" "=v")
(unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_TRUNC_ROUND_TO_ODD))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscvqpdpo %0,%1"
[(set_attr "type" "vecfloat")
(set_attr "size" "128")])
@@ -15555,7 +15554,7 @@
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:IEEE128 2 "altivec_register_operand"
"v")))]
- "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
+ "TARGET_FLOAT128_HW"
"xscmpuqp %0,%1,%2"
[(set_attr "type" "veccmp")
(set_attr "size" "128")])
