https://gcc.gnu.org/g:d64c5ffbfe1f13536d8cc5f6ffd2fbbdc3e1873c
commit d64c5ffbfe1f13536d8cc5f6ffd2fbbdc3e1873c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Jul 23 11:14:05 2024 -0400
Remove -mpower10 and -mpower8-internal
2024-07-23 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Remove
internal
options -mpower8-internal, -mpower10, and -mpower11.
(ISA_3_1_MASKS_SERVER): Likewise.
(POWER11_MASKS_SERVER): Likewise.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (TARGET_POWER8): Define in terms of
hardware
flags.
(TARGET_POWER10): Likewise.
* config/rs6000/rs6000.opt (-mpower8-internal): Do not create ISA
bit.
(-mpower10): Likewise.
(-mpower11): Delete.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 8 +-------
gcc/config/rs6000/rs6000.cc | 2 --
gcc/config/rs6000/rs6000.h | 5 +++++
gcc/config/rs6000/rs6000.opt | 11 ++---------
4 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 84fac8bdac1d..a3568898b0b6 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -47,7 +47,6 @@
fusion here, instead set it in rs6000.cc if we are tuning for a power8
system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
- | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
@@ -83,11 +82,9 @@
| OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
- | OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS)
-#define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
- | OPTION_MASK_POWER11)
+#define POWER11_MASKS_SERVER ISA_3_1_MASKS_SERVER
/* Flags that need to be turned off if -mno-vsx. */
#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
@@ -125,8 +122,6 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
- | OPTION_MASK_POWER10 \
- | OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
@@ -135,7 +130,6 @@
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
- | OPTION_MASK_POWER8 \
| OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 381d439c0cf3..4550fd44036e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -24526,8 +24526,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
- { "power10", OPTION_MASK_POWER10, false, true },
- { "power11", OPTION_MASK_POWER11, false, false },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2053de1fc176..548ef9c0fa50 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2517,3 +2517,8 @@ enum arch_bits {
#define ARCH_FLAGS_POWER9 (ARCH_FLAGS_POWER8 | ARCH_MASK_POWER9)
#define ARCH_FLAGS_POWER10 (ARCH_FLAGS_POWER9 | ARCH_MASK_POWER10)
#define ARCH_FLAGS_POWER11 (ARCH_FLAGS_POWER10 | ARCH_MASK_POWER11)
+
+/* We used to use -mpower8-internal and -mpower10 as an ISA bit, switch to use
+ an architecture bit. */
+#define TARGET_POWER8 ((rs6000_arch_flags & ARCH_MASK_POWER8) != 0)
+#define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0)
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 73dfb63a81ce..0d71dbaf2fc1 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -478,9 +478,8 @@ Save the TOC in the prologue for indirect calls rather than
inline.
mvsx-timode
Target RejectNegative Undocumented Ignore
-;; This option exists only to create its MASK. It is not intended for users.
mpower8-internal
-Target Undocumented Mask(POWER8) Var(rs6000_isa_flags) Warn(Do not use
%<-mpower8-internal%>; use %<-mcpu=power8%> instead)
+Target Undocumented WarnRemoved
mpower8-fusion
Target Mask(P8_FUSION) Var(rs6000_isa_flags)
@@ -591,13 +590,7 @@ mspeculate-indirect-jumps
Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
mpower10
-Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
-
-;; Users should not use -mpower11, but we need to use a bit to identify when
-;; the user changes the default cpu via #pragma GCC target("cpu=power11")
-;; and then resets it later.
-mpower11
-Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) WarnRemoved
+Target Undocumented WarnRemoved
mprefixed
Target Mask(PREFIXED) Var(rs6000_isa_flags)
