https://gcc.gnu.org/g:bd0fbdc30d831f8c84223f583bcb5e5f6d7d72fc
commit r12-10648-gbd0fbdc30d831f8c84223f583bcb5e5f6d7d72fc
Author: Haochen Jiang <haochen.ji...@intel.com>
Date: Thu Jul 25 16:12:20 2024 +0800
i386: Fix AVX512 intrin macro typo
There are several typo in AVX512 intrins macro define. Correct them to solve
errors when compiled with -O0.
gcc/ChangeLog:
* config/i386/avx512dqintrin.h
(_mm_mask_fpclass_ss_mask): Correct operand order.
(_mm_mask_fpclass_sd_mask): Ditto.
(_mm256_maskz_reduce_round_ss): Use
__builtin_ia32_reducess_mask_round
instead of __builtin_ia32_reducesd_mask_round.
(_mm_reduce_round_sd): Use -1 as mask since it is non-mask.
(_mm_reduce_round_ss): Ditto.
* config/i386/avx512vlbwintrin.h
(_mm256_mask_alignr_epi8): Correct operand usage.
(_mm_mask_alignr_epi8): Ditto.
* config/i386/avx512vlintrin.h (_mm_mask_alignr_epi64): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512bw-vpalignr-1b.c: New test.
* gcc.target/i386/avx512dq-vfpclasssd-1b.c: Ditto.
* gcc.target/i386/avx512dq-vfpclassss-1b.c: Ditto.
* gcc.target/i386/avx512dq-vreducesd-1b.c: Ditto.
* gcc.target/i386/avx512dq-vreducess-1b.c: Ditto.
* gcc.target/i386/avx512vl-valignq-1b.c: Ditto.
Diff:
---
gcc/config/i386/avx512dqintrin.h | 16 +++++++++-------
gcc/config/i386/avx512vlbwintrin.h | 4 ++--
gcc/config/i386/avx512vlintrin.h | 2 +-
gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-1b.c | 18 ++++++++++++++++++
gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1b.c | 14 ++++++++++++++
gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1b.c | 14 ++++++++++++++
gcc/testsuite/gcc.target/i386/avx512dq-vreducesd-1b.c | 16 ++++++++++++++++
gcc/testsuite/gcc.target/i386/avx512dq-vreducess-1b.c | 16 ++++++++++++++++
gcc/testsuite/gcc.target/i386/avx512vl-valignq-1b.c | 15 +++++++++++++++
9 files changed, 105 insertions(+), 10 deletions(-)
diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index e924250a4ad9..4f9451e949b5 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -2800,11 +2800,11 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), \
(int) (C), (__mmask8) (-1))) \
-#define _mm_mask_fpclass_ss_mask(X, C, U) \
+#define _mm_mask_fpclass_ss_mask(U, X, C) \
((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), \
(int) (C), (__mmask8) (U)))
-#define _mm_mask_fpclass_sd_mask(X, C, U) \
+#define _mm_mask_fpclass_sd_mask(U, X, C) \
((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), \
(int) (C), (__mmask8) (U)))
@@ -2839,8 +2839,9 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
(__mmask8)(U)))
#define _mm_reduce_round_sd(A, B, C, R) \
- ((__m128d) __builtin_ia32_reducesd_round ((__v2df)(__m128d)(A), \
- (__v2df)(__m128d)(B), (int)(C), (__mmask8)(U), (int)(R)))
+ ((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
+ (__v2df)(__m128d)(B), (int)(C), (__v2df) _mm_avx512_setzero_pd (), \
+ (__mmask8)(-1), (int)(R)))
#define _mm_mask_reduce_round_sd(W, U, A, B, C, R) \
((__m128d) __builtin_ia32_reducesd_mask_round ((__v2df)(__m128d)(A), \
@@ -2867,8 +2868,9 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
(__mmask8)(U)))
#define _mm_reduce_round_ss(A, B, C, R) \
- ((__m128) __builtin_ia32_reducess_round ((__v4sf)(__m128)(A), \
- (__v4sf)(__m128)(B), (int)(C), (__mmask8)(U), (int)(R)))
+ ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A), \
+ (__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_avx512_setzero_ps (), \
+ (__mmask8)(-1), (int)(R)))
#define _mm_mask_reduce_round_ss(W, U, A, B, C, R) \
((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A), \
@@ -2876,7 +2878,7 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm)
(__mmask8)(U), (int)(R)))
#define _mm_maskz_reduce_round_ss(U, A, B, C, R) \
- ((__m128) __builtin_ia32_reducesd_mask_round ((__v4sf)(__m128)(A), \
+ ((__m128) __builtin_ia32_reducess_mask_round ((__v4sf)(__m128)(A), \
(__v4sf)(__m128)(B), (int)(C), (__v4sf) _mm_setzero_ps (), \
(__mmask8)(U), (int)(R)))
diff --git a/gcc/config/i386/avx512vlbwintrin.h
b/gcc/config/i386/avx512vlbwintrin.h
index 192d54e743f7..c918ed520c5c 100644
--- a/gcc/config/i386/avx512vlbwintrin.h
+++ b/gcc/config/i386/avx512vlbwintrin.h
@@ -1839,7 +1839,7 @@ _mm_maskz_slli_epi16 (__mmask8 __U, __m128i __A, int __B)
#define _mm256_mask_alignr_epi8(W, U, X, Y, N)
\
((__m256i) __builtin_ia32_palignr256_mask ((__v4di)(__m256i)(X),
\
(__v4di)(__m256i)(Y), (int)((N) *
8), \
- (__v4di)(__m256i)(X),
(__mmask32)(U)))
+ (__v4di)(__m256i)(W),
(__mmask32)(U)))
#define _mm256_mask_srli_epi16(W, U, A, B) \
((__m256i) __builtin_ia32_psrlwi256_mask ((__v16hi)(__m256i)(A), \
@@ -1922,7 +1922,7 @@ _mm_maskz_slli_epi16 (__mmask8 __U, __m128i __A, int __B)
#define _mm_mask_alignr_epi8(W, U, X, Y, N)
\
((__m128i) __builtin_ia32_palignr128_mask ((__v2di)(__m128i)(X),
\
(__v2di)(__m128i)(Y), (int)((N) *
8), \
- (__v2di)(__m128i)(X),
(__mmask16)(U)))
+ (__v2di)(__m128i)(W),
(__mmask16)(U)))
#define _mm_maskz_alignr_epi8(U, X, Y, N)
\
((__m128i) __builtin_ia32_palignr128_mask ((__v2di)(__m128i)(X),
\
diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h
index 26b286eae6b7..c6f3f35a009e 100644
--- a/gcc/config/i386/avx512vlintrin.h
+++ b/gcc/config/i386/avx512vlintrin.h
@@ -13609,7 +13609,7 @@ _mm256_permutex_pd (__m256d __X, const int __M)
#define _mm_mask_alignr_epi64(W, U, X, Y, C) \
((__m128i)__builtin_ia32_alignq128_mask ((__v2di)(__m128i)(X), \
- (__v2di)(__m128i)(Y), (int)(C), (__v2di)(__m128i)(X), (__mmask8)-1))
+ (__v2di)(__m128i)(Y), (int)(C), (__v2di)(__m128i)(W), (__mmask8)(U)))
#define _mm_maskz_alignr_epi64(U, X, Y, C) \
((__m128i)__builtin_ia32_alignq128_mask ((__v2di)(__m128i)(X), \
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-1b.c
b/gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-1b.c
new file mode 100644
index 000000000000..2b42aa90b918
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-1b.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512bw -mavx512vl" } */
+/* { dg-final { scan-assembler-times "vpalignr\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpalignr\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i y;
+volatile __m128i x;
+volatile __mmask32 m2;
+volatile __mmask16 m3;
+
+void extern
+avx512bw_test (void)
+{
+ y = _mm256_mask_alignr_epi8 (y, m2, y, y, 10);
+ x = _mm_mask_alignr_epi8 (x, m3, x, x, 10);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1b.c
b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1b.c
new file mode 100644
index 000000000000..8c7f96fb7a70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1b.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512dq -O0" } */
+/* { dg-final { scan-assembler-times "vfpclasssd\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)"
1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x128;
+volatile __mmask8 m8;
+
+void extern
+avx512dq_test (void)
+{
+ m8 = _mm_mask_fpclass_sd_mask (m8, x128, 13);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1b.c
b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1b.c
new file mode 100644
index 000000000000..3196fd60d64b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1b.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512dq -O0" } */
+/* { dg-final { scan-assembler-times "vfpclassss\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)"
1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x128;
+volatile __mmask8 m8;
+
+void extern
+avx512dq_test (void)
+{
+ m8 = _mm_mask_fpclass_ss_mask (m8, x128, 13);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vreducesd-1b.c
b/gcc/testsuite/gcc.target/i386/avx512dq-vreducesd-1b.c
new file mode 100644
index 000000000000..9ae8259d373c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-vreducesd-1b.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512dq -O0" } */
+/* { dg-final { scan-assembler-times "vreducesd\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m128d x1, x2, xx1, xx2;
+volatile __mmask8 m;
+
+void extern
+avx512dq_test (void)
+{
+ xx1 = _mm_reduce_round_sd (xx1, xx2, IMM, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vreducess-1b.c
b/gcc/testsuite/gcc.target/i386/avx512dq-vreducess-1b.c
new file mode 100644
index 000000000000..47bf48fb6178
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-vreducess-1b.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512dq -O0" } */
+/* { dg-final { scan-assembler-times "vreducess\[
\\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m128 x1, x2, xx1, xx2;
+volatile __mmask8 m;
+
+void extern
+avx512dq_test (void)
+{
+ xx1 = _mm_reduce_round_ss (xx1, xx2, IMM, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-valignq-1b.c
b/gcc/testsuite/gcc.target/i386/avx512vl-valignq-1b.c
new file mode 100644
index 000000000000..0ab16b277338
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-valignq-1b.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512vl" } */
+/* { dg-final { scan-assembler-times "valignq\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i y;
+volatile __m128i x;
+volatile __mmask8 m;
+
+void extern
+avx512vl_test (void)
+{
+ x = _mm_mask_alignr_epi64 (x, m, x, x, 1);
+}
