[gcc r16-1779] RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 pipeline model [PR120659

[Kito Cheng via Gcc-cvs]

https://gcc.gnu.org/g:c8cb537fdbdbc9e1c77ec389bcb99ad87b15cb92

commit r16-1779-gc8cb537fdbdbc9e1c77ec389bcb99ad87b15cb92
Author: Kito Cheng <kito.ch...@sifive.com>
Date:   Tue Jun 17 16:20:19 2025 +0800

    RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7 
pipeline model [PR120659]
    
    gcc/ChangeLog:
    
            PR target/120659
            * config/riscv/sifive-7.md: Add B extension, fp16 and missing
            scalar instruction type for sifive-7 pipeline model.
    
    gcc/testsuite/ChangeLog:
    
            PR target/120659
            * gcc.target/riscv/pr120659.c: New test.

Diff:
---
 gcc/config/riscv/sifive-7.md              | 32 ++++++++++++++++++++++++++++---
 gcc/testsuite/gcc.target/riscv/pr120659.c |  5 +++++
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index c20854108893..b96d7eb8550e 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -60,9 +60,14 @@
 (define_insn_reservation "sifive_7_alu" 2
   (and (eq_attr "tune" "sifive_7")
        (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\
-                       
rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,mvpair,zicond"))
+                       min,max,minu,maxu,atomic,condmove,mvpair,zicond"))
   "sifive_7_A|sifive_7_B")
 
+(define_insn_reservation "sifive_7_alu_b" 2
+  (and (eq_attr "tune" "sifive_7")
+       (eq_attr "type" "clz,ctz,rotate"))
+  "sifive_7_B")
+
 (define_insn_reservation "sifive_7_load_immediate" 1
   (and (eq_attr "tune" "sifive_7")
        (eq_attr "type" "nop,const,auipc"))
@@ -91,6 +96,12 @@
        (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i,fcmp,fmove"))
   "sifive_7_B")
 
+(define_insn_reservation "sifive_7_fdiv_h" 14
+  (and (eq_attr "tune" "sifive_7")
+       (eq_attr "type" "fdiv,fsqrt")
+       (eq_attr "mode" "HF"))
+  "sifive_7_B,sifive_7_fpu*13")
+
 (define_insn_reservation "sifive_7_fdiv_s" 27
   (and (eq_attr "tune" "sifive_7")
        (eq_attr "type" "fdiv,fsqrt")
@@ -119,6 +130,21 @@
        (eq_attr "type" "cpop,clmul"))
   "sifive_7_A")
 
+(define_insn_reservation "sifive_7_csr" 5
+  (and (eq_attr "tune" "sifive_7")
+       (eq_attr "type" "rdfrm,wrfrm,wrvxrm"))
+  "sifive_7_A")
+
+(define_insn_reservation "sifive_7_crypto" 10
+  (and (eq_attr "tune" "sifive_7")
+       (eq_attr "type" "crypto"))
+  "sifive_7_A")
+
+(define_insn_reservation "sifive_7_unknown" 10
+  (and (eq_attr "tune" "sifive_7")
+       (eq_attr "type" "ghost"))
+  "sifive_7_A")
+
 (define_bypass 1 
"sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
   "sifive_7_alu,sifive_7_branch")
 
@@ -129,10 +155,10 @@
   "sifive_7_store" "riscv_store_data_bypass_p")
 
 (define_bypass 2 "sifive_7_i2f"
-  
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_s,sifive_7_fdiv_d")
+  
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_h,sifive_7_fdiv_s,sifive_7_fdiv_d,sifive_7_hfma")
 
 (define_bypass 2 "sifive_7_fp_other"
-  
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_s,sifive_7_fdiv_d")
+  
"sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_h,sifive_7_fdiv_s,sifive_7_fdiv_d,sifive_7_hfma")
 
 (define_bypass 2 "sifive_7_fp_other"
   "sifive_7_alu,sifive_7_branch")
diff --git a/gcc/testsuite/gcc.target/riscv/pr120659.c 
b/gcc/testsuite/gcc.target/riscv/pr120659.c
new file mode 100644
index 000000000000..91e6e42d4f95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr120659.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=sifive-x280 -mabi=lp64" } */
+
+_Float16 f;
+void foo() { f /= 3; }