https://gcc.gnu.org/g:3e74f60f117e7ef8211157b501810f6dc14cf2d8
commit 3e74f60f117e7ef8211157b501810f6dc14cf2d8
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Wed Jul 2 19:39:39 2025 -0400
Revert changes
Diff:
---
gcc/config/rs6000/rs6000.cc | 8 +-
gcc/config/rs6000/rs6000.md | 122 ++-------------------
gcc/testsuite/gcc.target/powerpc/float128-cmove.c | 6 +-
.../gcc.target/powerpc/float128-minmax-3.c | 6 +-
gcc/testsuite/gcc.target/powerpc/pr108958.c | 47 --------
gcc/testsuite/gcc.target/powerpc/pr118541-1.c | 28 -----
gcc/testsuite/gcc.target/powerpc/pr118541-2.c | 26 -----
gcc/testsuite/gcc.target/powerpc/pr120528.c | 91 ---------------
8 files changed, 12 insertions(+), 322 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 955a249d7a3e..7ee26e52b138 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16408,17 +16408,11 @@ rs6000_maybe_emit_fp_cmove (rtx dest, rtx op, rtx
true_cond, rtx false_cond)
/* Helper function to return true if the target has instructions to do a
compare and set mask instruction that can be used with XXSEL to implement a
conditional move. It is also assumed that such a target also supports the
- "C" minimum and maximum instructions.
-
- However, these instructions will trap if given a signaling NaN, so we can
- only use them if NaNs are not expected. */
+ "C" minimum and maximum instructions. */
static bool
have_compare_and_set_mask (machine_mode mode)
{
- if (!flag_finite_math_only)
- return false;
-
switch (mode)
{
case E_SFmode:
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c9182d80078c..9c718ca2a226 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -173,7 +173,6 @@
UNSPEC_XXSPLTIW_CONST
UNSPEC_FMAX
UNSPEC_FMIN
- UNSPEC_ZERO_EXTEND
])
;;
@@ -970,100 +969,6 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
-;; Optimize zero_extendsiti2 from a GPR to a GPR and then moving the GPR to a
-;; VSX register
-(define_peephole2
- [(set (match_operand:DI 0 "int_reg_operand")
- (match_operand:DI 1 "int_reg_operand"))
- (set (match_operand:DI 2 "int_reg_operand")
- (const_int 0))
- (set (match_operand:TI 3 "vsx_register_operand")
- (match_operand:TI 4 "int_reg_operand"))]
- "TARGET_DIRECT_MOVE_64BIT
- && (reg_or_subregno (operands[0])
- == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)
- && (reg_or_subregno (operands[2])
- == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)
- && peep2_reg_dead_p (3, operands[4])"
- [(set (match_dup 3)
- (unspec:TI [(match_dup 1)] UNSPEC_ZERO_EXTEND))])
-
-(define_insn "*zero_extendsiti2_vsx"
- [(set (match_operand:TI 0 "vsx_register_operand" "=wa")
- (unspec:TI [(match_operand:DI 1 "int_reg_operand" "r")]
- UNSPEC_ZERO_EXTEND))]
- "TARGET_DIRECT_MOVE_64BIT"
- "mtvsrdd %x0,0,%1"
- [(set_attr "type" "mtvsr")])
-
-;; On power10, optimize zero extending a QI/HI/SI/DImode value from memory that
-;; is going to a vector register target by generating a LXVR{B,H,W,D}X
-;; instruction without creating the TImode value in a GPR and using MTVSRDD to
-;; move it to the vector register.
-(define_peephole2
- [(set (match_operand:DI 0 "int_reg_operand")
- (match_operand:DI 1 "memory_operand"))
- (set (match_operand:DI 2 "base_reg_operand")
- (const_int 0))
- (set (match_operand:TI 3 "vsx_register_operand")
- (match_operand:TI 4 "int_reg_operand"))]
- "TARGET_POWER10 && TARGET_POWERPC64
- && (reg_or_subregno (operands[0])
- == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)
- && (reg_or_subregno (operands[2])
- == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)
- && peep2_reg_dead_p (3, operands[4])
- && (REG_P (XEXP (operands[1], 0))
- || SUBREG_P (XEXP (operands[1], 0))
- || GET_CODE (XEXP (operands[1], 0)) == PLUS)"
- [(set (match_dup 3)
- (zero_extend:TI (match_dup 5)))]
-{
- rtx mem = operands[1];
- rtx addr = XEXP (mem, 0);
-
- if (indexed_or_indirect_address (addr, DImode))
- operands[5] = mem;
- else
- {
- rtx op2 = operands[2];
- emit_insn (gen_rtx_SET (op2, addr));
- operands[5] = change_address (mem, DImode, op2);
- }
-})
-
-(define_peephole2
- [(set (match_operand:DI 0 "int_reg_operand")
- (zero_extend:DI
- (match_operand:QHSI 1 "memory_operand")))
- (set (match_operand:DI 2 "base_reg_operand")
- (const_int 0))
- (set (match_operand:TI 3 "vsx_register_operand")
- (match_operand:TI 4 "int_reg_operand"))]
- "TARGET_POWER10 && TARGET_POWERPC64
- && (reg_or_subregno (operands[0])
- == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)
- && (reg_or_subregno (operands[2])
- == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)
- && peep2_reg_dead_p (3, operands[4])
- && (REG_P (XEXP (operands[1], 0))
- || SUBREG_P (XEXP (operands[1], 0))
- || GET_CODE (XEXP (operands[1], 0)) == PLUS)"
- [(set (match_dup 3)
- (zero_extend:TI (match_dup 5)))]
-{
- rtx mem = operands[1];
- rtx addr = XEXP (mem, 0);
-
- if (indexed_or_indirect_address (addr, DImode))
- operands[5] = mem;
- else
- {
- rtx op2 = operands[2];
- emit_insn (gen_rtx_SET (op2, addr));
- operands[5] = change_address (mem, DImode, op2);
- }
-})
(define_insn "zero_extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
@@ -5748,10 +5653,6 @@
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
-;; On power9, we can generate XSCMP{EQ,GT,GE}DP and XXSEL to do a floating
-;; point conditional move. However, these instructions trap if one of the
-;; arguments is a signalling NaN. Therefore we can only do this optimize if
-;; NaNs are not expected in the code.
(define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
[(set (match_operand:SFDF 0 "vsx_register_operand" "=&wa,wa")
(if_then_else:SFDF
@@ -5761,7 +5662,7 @@
(match_operand:SFDF 4 "vsx_register_operand" "wa,wa")
(match_operand:SFDF 5 "vsx_register_operand" "wa,wa")))
(clobber (match_scratch:V2DI 6 "=0,&wa"))]
- "TARGET_P9_MINMAX && flag_finite_math_only"
+ "TARGET_P9_MINMAX"
"#"
"&& 1"
[(set (match_dup 6)
@@ -5793,7 +5694,7 @@
(match_operand:SFDF 4 "vsx_register_operand" "wa,wa")
(match_operand:SFDF 5 "vsx_register_operand" "wa,wa")))
(clobber (match_scratch:V2DI 6 "=0,&wa"))]
- "TARGET_P9_MINMAX && flag_finite_math_only"
+ "TARGET_P9_MINMAX"
"#"
"&& 1"
[(set (match_dup 6)
@@ -5828,7 +5729,7 @@
(match_operand:SFDF 3 "vsx_register_operand" "wa")])
(match_operand:V2DI 4 "all_ones_constant" "")
(match_operand:V2DI 5 "zero_constant" "")))]
- "TARGET_P9_MINMAX && flag_finite_math_only"
+ "TARGET_P9_MINMAX"
"xscmp%V1dp %x0,%x2,%x3"
[(set_attr "type" "fpcompare")])
@@ -5838,23 +5739,18 @@
(match_operand:V2DI 2 "zero_constant" ""))
(match_operand:SFDF 3 "vsx_register_operand" "wa")
(match_operand:SFDF 4 "vsx_register_operand" "wa")))]
- "TARGET_P9_MINMAX && flag_finite_math_only"
+ "TARGET_P9_MINMAX"
"xxsel %x0,%x4,%x3,%x1"
[(set_attr "type" "vecmove")])
;; Support for ISA 3.1 IEEE 128-bit conditional move. The mode used in the
;; comparison must be the same as used in the move.
-;;
-;; On power10, we can generate XSCMP{EQ,GT,GE}QP and XXSEL to do a floating
-;; point conditional move for IEEE 128-bit values. However, these instructions
-;; trap if one of the arguments is a signalling NaN. Therefore we can only do
-;; this optimize if NaNs are not expected in the code.
(define_expand "mov<mode>cc"
[(set (match_operand:IEEE128 0 "gpc_reg_operand")
(if_then_else:IEEE128 (match_operand 1 "comparison_operator")
(match_operand:IEEE128 2 "gpc_reg_operand")
(match_operand:IEEE128 3 "gpc_reg_operand")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && flag_finite_math_only"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
@@ -5871,7 +5767,7 @@
(match_operand:IEEE128 4 "altivec_register_operand" "v,v")
(match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
(clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && flag_finite_math_only"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 6)
@@ -5903,7 +5799,7 @@
(match_operand:IEEE128 4 "altivec_register_operand" "v,v")
(match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
(clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && flag_finite_math_only"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"#"
"&& 1"
[(set (match_dup 6)
@@ -5938,7 +5834,7 @@
(match_operand:IEEE128 3 "altivec_register_operand" "v")])
(match_operand:V2DI 4 "all_ones_constant" "")
(match_operand:V2DI 5 "zero_constant" "")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && flag_finite_math_only"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"xscmp%V1qp %0,%2,%3"
[(set_attr "type" "fpcompare")])
@@ -5949,7 +5845,7 @@
(match_operand:V2DI 2 "zero_constant" ""))
(match_operand:IEEE128 3 "altivec_register_operand" "v")
(match_operand:IEEE128 4 "altivec_register_operand" "v")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && flag_finite_math_only"
+ "TARGET_POWER10 && TARGET_FLOAT128_HW"
"xxsel %x0,%x4,%x3,%x1"
[(set_attr "type" "vecmove")])
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
index 496fe29740c8..2fae8dc23bcf 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
@@ -1,11 +1,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target ppc_float128_hw } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -Ofast" } */
-
-/* The XSCMP{EQ,GT,GE}QP instructions will trap if a signaling NaN is one of
- the arguments, so this code is now only generated if -Ofast or
- -ffinite-math-only is used. */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#ifndef TYPE
#ifdef __LONG_DOUBLE_IEEE128__
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
index 9c7474911981..6f7627c0f2a1 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
@@ -1,10 +1,6 @@
/* { dg-require-effective-target ppc_float128_hw } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -Ofast" } */
-
-/* The XS{MAX,MIN}}CQP instructions will trap if a signaling NaN is one of the
- arguments, so this code is now only generated if -Ofast or
- -ffinite-math-only is used. */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
#ifndef TYPE
#define TYPE _Float128
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108958.c
b/gcc/testsuite/gcc.target/powerpc/pr108958.c
deleted file mode 100644
index 21b3f2766918..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr108958.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target int128 } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-#ifndef TYPE
-#define TYPE unsigned long long
-#endif
-
-/* PR target/108958, when zero extending a DImode to a TImode, and the TImode
variable is in a VSX register, generate:
-
- mtvsrdd vreg,0,gpr
-
- instead of:
-
- mr tmp,gpr
- li tmp+1,0
- mtvsrdd vreg,tmp+1,tmp. */
-
-void
-gpr_to_vsx (TYPE x, __uint128_t *p)
-{
- /* mtvsrdd 0,0,3
- stvx 0,0(4) */
-
- __uint128_t y = x;
- __asm__ (" # %x0" : "+wa" (y));
- *p = y;
-}
-
-void
-gpr_to_gpr (TYPE x, __uint128_t *p)
-{
- /* mr 2,3
- li 3,0
- std 2,0(4)
- std 3,8(4) */
-
- __uint128_t y = x;
- __asm__ (" # %0" : "+r" (y));
- *p = y;
-}
-
-/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mmtvsrdd .*,0,.*\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstd\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstxv\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr118541-1.c
b/gcc/testsuite/gcc.target/powerpc/pr118541-1.c
deleted file mode 100644
index d5690dd7e38a..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr118541-1.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-/* { dg-require-effective-target powerpc_vsx } */
-
-/* PR target/118541 says that the ordered comparison functions like isgreater
- should not optimize floating point conditional moves to use
- x{s,v}cmp{eq,gt,ge}{dp,qp} and xxsel since that instruction can cause traps
- if one of the arguments is a signaling NaN. */
-
-/* Verify isgreater does not generate xscmpgtdp when NaNs are allowed. */
-
-double
-ordered_compare (double a, double b, double c, double d)
-{
- /*
- * fcmpu 0,1,2
- * fmr 1,4
- * bnglr 0
- * fmr 1,3
- * blr
- */
-
- return __builtin_isgreater (a, b) ? c : d;
-}
-
-/* { dg-final { scan-assembler-not {\mxscmpg[te]dp\M} } } */
-/* { dg-final { scan-assembler-not {\mxxsel\M} } } */
-/* { dg-final { scan-assembler {\mxscmpudp\M|\mfcmpu\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr118541-2.c
b/gcc/testsuite/gcc.target/powerpc/pr118541-2.c
deleted file mode 100644
index 5e1d83daedad..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr118541-2.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mdejagnu-cpu=power9 -Ofast" } */
-/* { dg-require-effective-target powerpc_vsx } */
-
-/* PR target/118541 says that the ordered comparison functions like isgreater
- should not optimize floating point conditional moves to use
- x{s,v}cmp{eq,gt,ge}{dp,qp} and xxsel since that instruction can cause traps
- if one of the arguments is a signaling NaN. */
-
-/* Verify isgreater does generate xscmpgtdp when NaNs are not allowed. */
-
-double
-ordered_compare (double a, double b, double c, double d)
-{
- /*
- * xscmpgtdp 1,1,2
- * xxsel 1,4,3,1
- * blr
- */
-
- return __builtin_isgreater (a, b) ? c : d;
-}
-
-/* { dg-final { scan-assembler {\mxscmpg[te]dp\M} } } */
-/* { dg-final { scan-assembler {\mxxsel\M} } } */
-/* { dg-final { scan-assembler-not {\mxscmpudp\M|\mfcmpu\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr120528.c
b/gcc/testsuite/gcc.target/powerpc/pr120528.c
deleted file mode 100644
index 476725eaa4fb..000000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr120528.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target int128 } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <stddef.h>
-
-#ifndef TYPE
-#define TYPE unsigned long long
-#endif
-
-void
-mem_to_vsx (TYPE *p, __uint128_t *q)
-{
- /* lxvrdx 0,0,3
- stxv 0,0(4) */
-
- __uint128_t x = *p;
- __asm__ (" # %x0" : "+wa" (x));
- *q = x;
-}
-
-void
-memx_to_vsx (TYPE *p, size_t n, __uint128_t *q)
-{
- /* sldi 4,4,3
- lxvrdx 0,3,4
- stxv 0,0(4) */
-
- __uint128_t x = p[n];
- __asm__ (" # %x0" : "+wa" (x));
- *q = x;
-}
-
-void
-mem3_to_vsx (TYPE *p, __uint128_t *q)
-{
- /* addi 2,3,24
- lxvrdx 0,0,2
- stxv 0,0(4) */
-
- __uint128_t x = p[3];
- __asm__ (" # %x0" : "+wa" (x));
- *q = x;
-}
-
-void
-mem_to_gpr (TYPE *p, __uint128_t *q)
-{
- /* ld 2,0(3)
- li 3,0
- std 2,0(4)
- std 3,8(8) */
-
- __uint128_t x = *p;
- __asm__ (" # %0" : "+r" (x));
- *q = x;
-}
-
-void
-memx_to_gpr (TYPE *p, size_t n, __uint128_t *q)
-{
- /* sldi 4,4,3
- ldx 2,3,4
- li 3,0
- std 2,0(4)
- std 3,8(8) */
-
- __uint128_t x = p[n];
- __asm__ (" # %0" : "+r" (x));
- *q = x;
-}
-
-void
-mem3_to_gpr (TYPE *p, __uint128_t *q)
-{
- /* ld 2,24(3)
- li 3,0
- std 2,0(4)
- std 3,8(8) */
-
- __uint128_t x = p[3];
- __asm__ (" # %0" : "+r" (x));
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\maddi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mli\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mlxvrdx\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mstxv\M} 3 } } */
