https://gcc.gnu.org/g:626d67f0fb9696434152de97e80b2c0a7e85f15a

commit r16-2425-g626d67f0fb9696434152de97e80b2c0a7e85f15a
Author: Karl Meakin <karl.mea...@arm.com>
Date:   Tue Jul 15 14:49:57 2025 +0000

    AArch64: precommit test for masked load vectorisation.
    
    Commit the test file `mask_load_2.c` before the vectorisation analysis
    is changed, so that the changes in codegen are more obvious in the next
    commit.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/aarch64/sve/mask_load_2.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c 
b/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c
new file mode 100644
index 000000000000..38fcf4f72060
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c
@@ -0,0 +1,23 @@
+// { dg-do compile }
+// { dg-options "-march=armv8-a+sve -msve-vector-bits=128 -O3" }
+
+typedef struct Array {
+    int elems[3];
+} Array;
+
+int loop(Array **pp, int len, int idx) {
+    int nRet = 0;
+
+    #pragma GCC unroll 0
+    for (int i = 0; i < len; i++) {
+        Array *p = pp[i];
+        if (p) {
+            nRet += p->elems[idx];
+        }
+    }
+
+    return nRet;
+}
+
+// { dg-final { scan-assembler-times {ld1w\tz[0-9]+\.d, p[0-7]/z} 0 } }
+// { dg-final { scan-assembler-times {add\tz[0-9]+\.s, p[0-7]/m}  0 } }

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