[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:cef5e1ca9d07d081e2a218404198bab416562762

commit cef5e1ca9d07d081e2a218404198bab416562762
Author: Jeff Law <j...@ventanamicro.com>
Date:   Sat Jun 21 08:24:58 2025 -0600

    [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V
    
    The RISC-V prefetch support is broken in a few ways.  This addresses the 
data
    side prefetch problems.  I'd mistakenly thought this BZ was a prefetch.i
    related (which has deeper problems).
    
    The basic problem is we were accepting any valid address when in fact there 
are
    restrictions.  This patch more precisely defines the predicate such that we
    allow
    
    REG
    REG+D
    
    Where D must have the low 5 bits clear.  Note that absolute addresses fall 
into
    the REG+D form using the x0 for the register operand since it always has the
    value zero.  The test verifies REG, REG+D, ABS addressing modes that are 
valid
    as well as REG+D and ABS which must be reloaded into a REG because the
    displacement has low bits set.
    
    An earlier version of this patch has gone through testing in my tester on 
rv32
    and rv64.  Obviously I'll wait for pre-commit CI to do its thing before 
moving
    forward.
    
    This is a good backport candidate after simmering on the trunk for a bit.
    
            PR target/118241
    gcc/
            * config/riscv/predicates.md (prefetch_operand): New predicate.
            * config/riscv/constraints.md (Q): New constraint.
            * config/riscv/riscv.md (prefetch): Use new predicate and 
constraint.
            (riscv_prefetchi_<mode>): Similarly.
    
    gcc/testsuite/
            * gcc.target/riscv/pr118241.c: New test.
    
    (cherry picked from commit 49199bb29628365fc6c60bd185808a1bad65086d)

Diff:
---
 gcc/config/riscv/constraints.md | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 58355cf03f2f..ccab1a2e29df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -325,3 +325,7 @@
   "A 2-bit unsigned immediate."
   (and (match_code "const_int")
        (match_test "IN_RANGE (ival, 0, 3)")))
+
+(define_constraint "Q"
+  "An address operand that is valid for a prefetch instruction"
+  (match_operand 0 "prefetch_operand"))