[gcc r15-10297] RISC-V: Check if we can vec_extract [PR121510].

[Robin Dapp via Gcc-cvs]

https://gcc.gnu.org/g:1c824f038848870219105a5fa16c48a2e0746643

commit r15-10297-g1c824f038848870219105a5fa16c48a2e0746643
Author: Robin Dapp <rd...@ventanamicro.com>
Date:   Fri Sep 5 09:35:46 2025 +0200

    RISC-V: Check if we can vec_extract [PR121510].
    
    For Zvfhmin a vector mode exists but the corresponding vec_extract does
    not.  This patch checks that a vec_extract is available and otherwise
    falls back to standard handling.
    
            PR target/121510
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.cc (riscv_legitimize_move): Check if we can
            vec_extract.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/pr121510.c: New test.
    
    (cherry picked from commit a6bf07653cd272add46a2218ec141c95d7f02427)

Diff:
---
 gcc/config/riscv/riscv.cc                             |  3 ++-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c | 18 ++++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 031584a437a9..472c2e60d9f5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3596,7 +3596,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
       /* This test can fail if (for example) we want a HF and Z[v]fh is
         not enabled.  In that case we just want to let the standard
         expansion path run.  */
-      if (riscv_vector::get_vector_mode (smode, nunits).exists (&vmode))
+      if (riscv_vector::get_vector_mode (smode, nunits).exists (&vmode)
+         && convert_optab_handler (vec_extract_optab, vmode, smode))
        {
          rtx v = gen_lowpart (vmode, SUBREG_REG (src));
          rtx int_reg = dest;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c
new file mode 100644
index 000000000000..8e1728608d3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr121510.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3" } */
+
+long *print_bfloat_block;
+void ftoastr(float);
+void print_bfloat() {
+  for (;;) {
+    long j;
+    union {
+      _Float16 x;
+      char b[]
+    } u;
+    j = 0;
+    for (; j < sizeof 0; j++)
+      u.b[j] = print_bfloat_block[j];
+    ftoastr(u.x);
+  }
+}