https://gcc.gnu.org/g:34978983845fd87f29a83edd99cf16cd5f558185
commit 34978983845fd87f29a83edd99cf16cd5f558185
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Tue Sep 9 19:18:55 2025 -0400
Revert changes
Diff:
---
gcc/ChangeLog.float | 47 ++-----------------------------------
gcc/config/rs6000/altivec.md | 12 +++++-----
gcc/config/rs6000/rs6000-builtin.cc | 2 --
gcc/config/rs6000/rs6000-modes.def | 2 +-
gcc/config/rs6000/rs6000.cc | 30 +++--------------------
gcc/config/rs6000/rs6000.h | 7 +-----
gcc/config/rs6000/rs6000.md | 39 +++++++-----------------------
gcc/config/rs6000/vector.md | 10 ++++----
gcc/config/rs6000/vsx.md | 28 +++++++++++-----------
9 files changed, 41 insertions(+), 136 deletions(-)
diff --git a/gcc/ChangeLog.float b/gcc/ChangeLog.float
index e00ce89f6cda..9da1dc3e76e2 100644
--- a/gcc/ChangeLog.float
+++ b/gcc/ChangeLog.float
@@ -1,48 +1,5 @@
-==================== Branch work221-float, patch #306 ====================
-
-Remove bfloat16 for now.
-
-2025-09-09 Michael Meissner <meiss...@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/altivec.md (VM): Remove bfloat16 support.
- (VM2): Likewise.
- (VI_char): Likewise.
- (VI_scalar): Likewise.
- (VI_unit): Likewise.
- (VU_char): Likewise.
- * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Likewise.
- * config/rs6000/rs6000-modes.def (BFmode): Likewise.
- * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Likewise.
- (rs6000_setup_reg_addr_masks): Likewise.
- (rs6000_init_hard_regno_mode_ok): Likewise.
- * config/rs6000/rs6000.h (FP16_SCALAR_P): Likewise.
- * config/rs6000/rs6000.md (FMOVE128_GPR): Likewise.
- (RELOAD): Likewise.
- (extendbf<mode>2): Likewise.
- (trunc<mode>bf2): Likewise.
- * config/rs6000/vector.md (VEC_L): Likewise.
- (VEC_M): Likewise.
- (VEC_E): Likewise.
- (VEC_base): Likewise.
- (VEC_base_l): Likewise.
- (V8HI_V8HF): Likewise.
- (VSX_L): Likewise.
- (VSX_M): Likewise.
- (VSX_XXBR): Likewise.
- (VSm): Likewise.
- (VSr): Likewise.
- (VSisa): Likewise.
- (??r): Likewise.
- (nW): Likewise.
- (VSv): Likewise.
- (VM3): Likewise.
- (VM3_char): Likewise.
- (vsx_extract_<mode>_store_p9): Likewise.
- (vsx_extract_<mode>_p8): Likewise.
-
-==================== Branch work221-float, patch #305 ====================
+==================== Branch work221-float, patch #306 was reverted
====================
+==================== Branch work221-float, patch #305 was reverted
====================
Attempt to fix bfloat16 problems.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 4c384642a624..fb960f7ba966 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -189,9 +189,9 @@
(define_mode_iterator V [V4SI V8HI V16QI V4SF])
;; Vec modes for move/logical/permute ops, include vector types for move not
;; otherwise handled by altivec (v2df, v2di, ti)
-;; V8BF
(define_mode_iterator VM [V4SI
V8HI
+ V8BF
V8HF
V16QI
V4SF
@@ -203,9 +203,9 @@
(TF "FLOAT128_VECTOR_P (TFmode)")])
;; Like VM, except don't do TImode
-;; V8BF
(define_mode_iterator VM2 [V4SI
V8HI
+ V8BF
V8HF
V16QI
V4SF
@@ -226,21 +226,21 @@
V1TI
TI])
-;; (V8BF "h")
(define_mode_attr VI_char [(V2DI "d")
(V4SI "w")
(V8HI "h")
+ (V8BF "h")
(V8HF "h")
(V16QI "b")])
-;; (V8BF "BF")
(define_mode_attr VI_scalar [(V2DI "DI")
(V4SI "SI")
(V8HI "HI")
+ (V8BF "BF")
(V8HF "HF")
(V16QI "QI")])
-;; (V8BF "VECTOR_UNIT_ALTIVEC_P (V8BFmode)")
(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)")
(V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)")
+ (V8BF "VECTOR_UNIT_ALTIVEC_P (V8BFmode)")
(V8HF "VECTOR_UNIT_ALTIVEC_P (V8HFmode)")
(V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)")
(V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")])
@@ -253,10 +253,10 @@
(define_mode_attr VP_small_lc [(V2DI "v4si")
(V4SI "v8hi")
(V8HI "v16qi")])
-;; (V8BF "b")
(define_mode_attr VU_char [(V2DI "w")
(V4SI "h")
(V8HI "b")
+ (V8BF "b")
(V8HF "b")])
;; Vector negate
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 2fede96d5b66..46c781b82568 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -761,7 +761,6 @@ rs6000_init_builtins (void)
ieee128_float_type_node = NULL_TREE;
/* __bfloat16 support. */
-#if 0
if (TARGET_BFLOAT16)
{
bfloat16_type_node = make_node (REAL_TYPE);
@@ -772,7 +771,6 @@ rs6000_init_builtins (void)
lang_hooks.types.register_builtin_type (bfloat16_type_node,
"__bfloat16");
}
-#endif
/* Vector pair and vector quad support. */
vector_pair_type_node = make_node (OPAQUE_TYPE);
diff --git a/gcc/config/rs6000/rs6000-modes.def
b/gcc/config/rs6000/rs6000-modes.def
index 218c4e83954e..28eb389787ff 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -49,7 +49,7 @@ FLOAT_MODE (IF, 16, ibm_extended_format);
FLOAT_MODE (HF, 2, ieee_half_format);
/* Arm (google brain) 16-bit floating point. */
-/* FLOAT_MODE (BF, 2, arm_bfloat_half_format); */
+FLOAT_MODE (BF, 2, arm_bfloat_half_format);
/* Add any extra modes needed to represent the condition code.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 39b1e71c98a1..a350eeca6dbe 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2258,7 +2258,7 @@ rs6000_debug_reg_global (void)
DImode,
TImode,
PTImode,
- // BFmode,
+ BFmode,
HFmode,
SFmode,
DFmode,
@@ -2280,7 +2280,7 @@ rs6000_debug_reg_global (void)
V8SImode,
V4DImode,
V2TImode,
- // V8BFmode,
+ V8BFmode,
V8HFmode,
V4SFmode,
V2DFmode,
@@ -2697,7 +2697,7 @@ rs6000_setup_reg_addr_masks (void)
&& (m != E_DFmode || !TARGET_VSX)
&& (m != E_SFmode || !TARGET_P8_VECTOR)
&& m != E_HFmode
- // && m != E_BFmode
+ && m != E_BFmode
&& !small_int_vsx_p)
{
addr_mask |= RELOAD_REG_PRE_INCDEC;
@@ -2953,14 +2953,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_vector_align[V8HFmode] = align64;
}
-#if 0
if (TARGET_BFLOAT16)
{
rs6000_vector_unit[V8BFmode] = VECTOR_VSX;
rs6000_vector_mem[V8BFmode] = VECTOR_VSX;
rs6000_vector_align[V8BFmode] = align64;
}
-#endif
/* DFmode, see if we want to use the VSX unit. Memory is handled
differently, so don't set rs6000_vector_mem. */
@@ -2991,13 +2989,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_vector_align[HFmode] = 16;
}
-#if 0
if (TARGET_BFLOAT16)
{
rs6000_vector_mem[BFmode] = VECTOR_VSX;
rs6000_vector_align[BFmode] = 16;
}
-#endif
/* Add support for vector pairs and vector quad registers. */
if (TARGET_MMA)
@@ -3058,10 +3054,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
-#if 0
reg_addr[V8BFmode].reload_store = CODE_FOR_reload_v8bf_di_store;
reg_addr[V8BFmode].reload_load = CODE_FOR_reload_v8bf_di_load;
-#endif
reg_addr[V8HFmode].reload_store = CODE_FOR_reload_v8hf_di_store;
reg_addr[V8HFmode].reload_load = CODE_FOR_reload_v8hf_di_load;
reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
@@ -3099,13 +3093,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[HFmode].reload_load = CODE_FOR_reload_hf_di_load;
}
-#if 0
if (TARGET_BFLOAT16)
{
reg_addr[BFmode].reload_store = CODE_FOR_reload_bf_di_store;
reg_addr[BFmode].reload_load = CODE_FOR_reload_bf_di_load;
}
-#endif
/* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
available. */
@@ -3129,10 +3121,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[V2DImode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxv2di;
reg_addr[V4SFmode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxv4sf;
reg_addr[V4SImode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxv4si;
-#if 0
reg_addr[V8BFmode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxv8bf;
reg_addr[V8HFmode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxv8hf;
-#endif
reg_addr[V8HImode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxv8hi;
reg_addr[V16QImode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxv16qi;
reg_addr[SFmode].reload_gpr_vsx =
CODE_FOR_reload_gpr_from_vsxsf;
@@ -3143,10 +3133,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[V2DImode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprv2di;
reg_addr[V4SFmode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprv4sf;
reg_addr[V4SImode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprv4si;
-#if 0
reg_addr[V8BFmode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprv8bf;
reg_addr[V8HFmode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprv8hf;
-#endif
reg_addr[V8HImode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprv8hi;
reg_addr[V16QImode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprv16qi;
reg_addr[SFmode].reload_vsx_gpr =
CODE_FOR_reload_vsx_from_gprsf;
@@ -3184,10 +3172,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
-#if 0
reg_addr[V8BFmode].reload_store = CODE_FOR_reload_v8bf_si_store;
reg_addr[V8BFmode].reload_load = CODE_FOR_reload_v8bf_si_load;
-#endif
reg_addr[V8HFmode].reload_store = CODE_FOR_reload_v8hf_si_store;
reg_addr[V8HFmode].reload_load = CODE_FOR_reload_v8hf_si_load;
reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
@@ -3219,13 +3205,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[HFmode].reload_load = CODE_FOR_reload_hf_si_load;
}
-#if 0
if (TARGET_BFLOAT16)
{
reg_addr[BFmode].reload_store = CODE_FOR_reload_bf_si_store;
reg_addr[BFmode].reload_load = CODE_FOR_reload_bf_si_load;
}
-#endif
/* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
available. */
@@ -3968,14 +3952,6 @@ rs6000_option_override_internal (bool global_init_p)
}
}
- /* -mbfloat16 needs -mcpu=power10. */
- if (TARGET_BFLOAT16 && !TARGET_POWER10)
- {
- rs6000_isa_flags &= ~OPTION_MASK_BFLOAT16;
- if ((rs6000_isa_flags_explicit & OPTION_MASK_BFLOAT16) != 0)
- warning (0, "%qs needs at least %qs", "-mbfloat16", "-mcpu=power10");
- }
-
/* If hard-float/altivec/vsx were explicitly turned off then don't allow
the -mcpu setting to enable options that conflict. */
if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 72bc3dd57928..98c3ae93fa08 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -572,14 +572,9 @@ extern int rs6000_vector_align[];
convert vector __bfloat16 formats. */
#define TARGET_IEEE16 TARGET_P9_VECTOR
-#if 0
#define FP16_SCALAR_P(MODE) \
(((MODE) == HFmode && TARGET_IEEE16) \
- || ((MODE) == BFmode && TARGET_BFLOAT16))
-
-#else
-#define FP16_SCALAR_P(MODE) ((MODE) == HFmode && TARGET_IEEE16)
-#endif
+ || ((MODE) == BFmode && TARGET_BFLOAT16 && TARGET_POWER10))
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c5c55e27191d..c6b6d7e9ad54 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -549,10 +549,10 @@
(TD "TARGET_HARD_FLOAT")])
; Iterators for 128 bit types for direct move
-;; V8BF
(define_mode_iterator FMOVE128_GPR [TI
V16QI
V8HI
+ V8BF
V8HF
V4SI
V4SF
@@ -839,9 +839,8 @@
;; Reload iterator for creating the function to allocate a base register to
;; supplement addressing modes.
-;; V8BF BF
-(define_mode_iterator RELOAD [V16QI V8HI V8HF V4SI V2DI V4SF V2DF V1TI
- SF SD SI DF DD DI TI PTI KF IF TF HF
+(define_mode_iterator RELOAD [V16QI V8HI V8BF V8HF V4SI V2DI V4SF V2DF V1TI
+ SF SD SI DF DD DI TI PTI KF IF TF BF HF
OO XO])
;; Iterate over smin, smax
@@ -861,8 +860,7 @@
(DI "TARGET_POWERPC64")])
;; Mode iterator for supported 16-bit floating point types.
-;; (BF "TARGET_BFLOAT16")
-(define_mode_iterator FP16 [(HF "TARGET_IEEE16")])
+(define_mode_iterator FP16 [HF BF])
;; Mode iterator for floating point modes other than SF/DFmode that we
;; convert to/from _Float16 (HFmode) via DFmode.
@@ -5879,26 +5877,6 @@
"xscvdphp %x0,%1"
[(set_attr "type" "fpsimple")])
-;; (define_insn "extendbf<mode>2"
-;; [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa")
-;; (float_extend:SFDF
-;; (match_operand:BF 1 "vsx_register_operand" "wa")))]
-;; "TARGET_BFLOAT16"
-;; {
-;; return "foo-xscvhpdp %x0,%x1";
-;; }
-;; [(set_attr "type" "fpsimple")])
-;;
-;; (define_insn "trunc<mode>bf2"
-;; [(set (match_operand:BF 0 "vsx_register_operand" "=wa")
-;; (float_truncate:BF
-;; (match_operand:SFDF 1 "vsx_register_operand" "wa")))]
-;; "TARGET_BFLOAT16"
-;; {
-;; return "foo-xscvdphp %x0,%1";
-;; }
-;; [(set_attr "type" "fpsimple")])
-
;; Use DFmode to convert to/from HFmode for floating point types other
;; than SF/DFmode.
(define_expand "extendhf<mode>2"
@@ -8226,7 +8204,7 @@
(define_expand "mov<mode>"
[(set (match_operand:FP16 0 "nonimmediate_operand")
(match_operand:FP16 1 "any_operand"))]
- ""
+ "FP16_SCALAR_P (<MODE>mode)"
{
if (MEM_P (operands[0]) && !REG_P (operands[1]))
operands[1] = force_reg (<MODE>mode, operands[1]);
@@ -8237,7 +8215,7 @@
(define_insn "*mov<mode>_xxspltiw"
[(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r")
(match_operand:FP16 1 "fp16_xxspltiw_constant" "eP,eP"))]
- "TARGET_POWER10 && TARGET_PREFIXED"
+ "FP16_SCALAR_P (<MODE>mode) && TARGET_POWER10 && TARGET_PREFIXED"
{
rtx op1 = operands[1];
const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op1);
@@ -8260,8 +8238,9 @@
(match_operand:FP16 1 "any_operand"
"wa, Z, wa, r, m,
r, wa, r, j, j"))]
- "(gpc_reg_operand (operands[0], <MODE>mode)
- || gpc_reg_operand (operands[1], <MODE>mode))"
+ "FP16_SCALAR_P (<MODE>mode)
+ && (gpc_reg_operand (operands[0], <MODE>mode)
+ || gpc_reg_operand (operands[1], <MODE>mode))"
"@
xxlor %x0,%x1,%x1
lxsihzx %x0,%y1
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 9f9634752cf9..0a9f092c1951 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -50,9 +50,9 @@
(define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
;; Vector logical modes
-;; V8BF
(define_mode_iterator VEC_L [V16QI
V8HI
+ V8BF
V8HF
V4SI
V2DI
@@ -65,11 +65,11 @@
;; Vector modes for moves. Don't do TImode or TFmode here, since their
;; moves are handled elsewhere.
-;; V8BF
(define_mode_iterator VEC_M [V16QI
V8HI
V4SI
V2DI
+ V8BF
V8HF
V4SF
V2DF
@@ -83,11 +83,11 @@
(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])
;; Vector init/extract modes
-;; V8BF
(define_mode_iterator VEC_E [V16QI
V8HI
V4SI
V2DI
+ V8BF
V8HF
V4SF
V2DF])
@@ -99,11 +99,11 @@
(define_mode_iterator VI [V4SI V8HI V16QI])
;; Base type from vector mode
-;; (V8BF "BF")
(define_mode_attr VEC_base [(V16QI "QI")
(V8HI "HI")
(V4SI "SI")
(V2DI "DI")
+ (V8BF "BF")
(V8HF "HF")
(V4SF "SF")
(V2DF "DF")
@@ -111,11 +111,11 @@
(TI "TI")])
;; As above, but in lower case
-;; (V8BF "bf")
(define_mode_attr VEC_base_l [(V16QI "qi")
(V8HI "hi")
(V4SI "si")
(V2DI "di")
+ (V8BF "bf")
(V8HF "hf")
(V4SF "sf")
(V2DF "df")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a8185db949b2..be65b309c63a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -47,14 +47,14 @@
(define_mode_iterator VSX_F [V4SF V2DF])
;; Iterator for 8 element vectors
-;; (V8BF "TARGET_BFLOAT16")
(define_mode_iterator V8HI_V8HF [V8HI
+ (V8BF "TARGET_BFLOAT16")
(V8HF "TARGET_IEEE16")])
;; Iterator for logical types supported by VSX
-;; (V8BF "TARGET_BFLOAT16")
(define_mode_iterator VSX_L [V16QI
V8HI
+ (V8BF "TARGET_BFLOAT16")
(V8HF "TARGET_IEEE16")
V4SI
V2DI
@@ -66,9 +66,9 @@
(TF "FLOAT128_VECTOR_P (TFmode)")])
;; Iterator for memory moves.
-;; (V8BF "TARGET_BFLOAT16<")
(define_mode_iterator VSX_M [V16QI
V8HI
+ (V8BF "TARGET_BFLOAT16")
(V8HF "TARGET_IEEE16")
V4SI
V2DI
@@ -79,8 +79,8 @@
(TF "FLOAT128_VECTOR_P (TFmode)")
TI])
-;; (V8BF "h")
(define_mode_attr VSX_XXBR [(V8HI "h")
+ (V8BF "h")
(V8HF "h")
(V4SI "w")
(V4SF "w")
@@ -89,9 +89,9 @@
(V1TI "q")])
;; Map into the appropriate load/store name based on the type
-;; (V8BF "vw4")
(define_mode_attr VSm [(V16QI "vw4")
(V8HI "vw4")
+ (V8BF "vw4")
(V8HF "vw4")
(V4SI "vw4")
(V4SF "vw4")
@@ -104,9 +104,9 @@
(TI "vd2")])
;; Map the register class used
-;; (V8BF "v")
(define_mode_attr VSr [(V16QI "v")
(V8HI "v")
+ (V8BF "v")
(V8HF "v")
(V4SI "v")
(V4SF "wa")
@@ -121,9 +121,9 @@
(TI "wa")])
;; What value we need in the "isa" field, to make the IEEE QP float work.
-;; (V8BF "p10")
(define_mode_attr VSisa [(V16QI "*")
(V8HI "*")
+ (V8BF "p10")
(V8HF "p9v")
(V4SI "*")
(V4SF "*")
@@ -139,9 +139,9 @@
;; A mode attribute to disparage use of GPR registers, except for scalar
;; integer modes.
-;; (V8BF "??r")
(define_mode_attr ??r [(V16QI "??r")
(V8HI "??r")
+ (V8BF "??r")
(V8HF "??r")
(V4SI "??r")
(V4SF "??r")
@@ -153,9 +153,9 @@
(TI "r")])
;; A mode attribute used for 128-bit constant values.
-;; (V8BF "W")
(define_mode_attr nW [(V16QI "W")
(V8HI "W")
+ (V8BF "W")
(V8HF "W")
(V4SI "W")
(V4SF "W")
@@ -182,9 +182,9 @@
;; Map into either s or v, depending on whether this is a scalar or vector
;; operation
-;; (V8BF "v")
(define_mode_attr VSv [(V16QI "v")
(V8HI "v")
+ (V8BF "v")
(V8HF "v")
(V4SI "v")
(V4SF "v")
@@ -417,9 +417,9 @@
(V2DI "8") (V2DF "8")])
;; Like VM2 in altivec.md, just do char, short, int, long, float and double
-;; V8BF
(define_mode_iterator VM3 [V4SI
V8HI
+ V8BF
V8HF
V16QI
V4SF
@@ -429,10 +429,10 @@
(define_mode_attr DI_to_TI [(V2DI "V1TI")
(DI "TI")])
-;; (V8BF "h")
(define_mode_attr VM3_char [(V2DI "d")
(V4SI "w")
(V8HI "h")
+ (V8BF "h")
(V8HF "h")
(V16QI "b")
(V2DF "d")
@@ -4108,7 +4108,7 @@
&& ((<MODE>mode == V16QImode
&& INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 7 : 8))
|| ((<MODE>mode == V8HImode || <MODE>mode == V8HFmode
- /* || <MODE>mode == V8BFmode */)
+ || <MODE>mode == V8BFmode)
&& INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 3 : 4))))
{
enum machine_mode dest_mode = GET_MODE (operands[0]);
@@ -4188,7 +4188,7 @@
vec_tmp = src;
}
else if (<MODE>mode == V8HImode || <MODE>mode == V8HFmode
- /* || <MODE>mode == V8BFmode */)
+ || <MODE>mode == V8BFmode)
{
if (value != 3)
emit_insn (gen_altivec_vsplth_direct (vec_tmp, src, element));
