https://gcc.gnu.org/g:e69688d1c0d368e893e031e8d3104de1d29bbf7c
commit e69688d1c0d368e893e031e8d3104de1d29bbf7c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Thu Sep 11 01:43:50 2025 -0400
Add -mbfloat16 switch.
2025-09-11 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/altivec.md (VM): Add initial bfloat16 support.
(VM2): Likewise.
(VI_char): Likewise.
(VI_scalar): Likewise.
(VI_unit): Likewise.
(VU_char): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Likewise.
(rs6000_init_builtins): Likewise.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Likewise.
* config/rs6000/rs6000-modes.def (BFmode): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.md (FMOVE128_GPR): Likewise.
(RELOAD): Likewise.
(FP16): New mode iterator.
(mov<mode>, FP16 iterator): Rename insns, to support both HFmode and
BFmode moves.
(mov<mode>_xxsplti): Likewise.
(mov<mode>_internal, FP16 iterator): Likewise.
* config/rs6000/rs6000.opt (-mbfloat16): New switch.
* config/rs6000/vector.md (VEC_L): Add initial __bfloat16 support.
(VEC_M): Likewise.
(VEC_E): Likewise.
(VEC_base): Likewise.
(VEC_base_l): Likewise.
* config/rs6000/vsx.md (VECTOR_16BIT): Rename from V8HI_V8HF and add
bfloat16 support.
(VSX_L): Likewise.
(VSX_M): Likewise.
(VSX_XXBR): Likewise.
(VSm): Likewise.
(VSr): Likewise.
(VSisa): Likewise.
(??r): Likewise.
(nW): Likewise.
(VSv): Likewise.
(VM3): Likewise.
(VM3_char): Likewise.
(vsx_extract_<mode>_store_p9): Likewise.
(vsx_extract_<mode>_p8): Likewise.
Diff:
---
gcc/config/rs6000/altivec.md | 6 +++
gcc/config/rs6000/rs6000-builtin.cc | 14 ++++++
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000-modes.def | 3 ++
gcc/config/rs6000/rs6000.cc | 9 ++++
gcc/config/rs6000/rs6000.md | 45 ++++++++++--------
gcc/config/rs6000/rs6000.opt | 4 ++
gcc/config/rs6000/vector.md | 5 ++
gcc/config/rs6000/vsx.md | 94 +++++++++++++++++++++----------------
9 files changed, 121 insertions(+), 60 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index b6f92a71f963..fb960f7ba966 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -191,6 +191,7 @@
;; otherwise handled by altivec (v2df, v2di, ti)
(define_mode_iterator VM [V4SI
V8HI
+ V8BF
V8HF
V16QI
V4SF
@@ -204,6 +205,7 @@
;; Like VM, except don't do TImode
(define_mode_iterator VM2 [V4SI
V8HI
+ V8BF
V8HF
V16QI
V4SF
@@ -227,15 +229,18 @@
(define_mode_attr VI_char [(V2DI "d")
(V4SI "w")
(V8HI "h")
+ (V8BF "h")
(V8HF "h")
(V16QI "b")])
(define_mode_attr VI_scalar [(V2DI "DI")
(V4SI "SI")
(V8HI "HI")
+ (V8BF "BF")
(V8HF "HF")
(V16QI "QI")])
(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)")
(V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)")
+ (V8BF "VECTOR_UNIT_ALTIVEC_P (V8BFmode)")
(V8HF "VECTOR_UNIT_ALTIVEC_P (V8HFmode)")
(V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)")
(V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")])
@@ -251,6 +256,7 @@
(define_mode_attr VU_char [(V2DI "w")
(V4SI "h")
(V8HI "b")
+ (V8BF "b")
(V8HF "b")])
;; Vector negate
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 05a730a8fdca..845adcdae8e6 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -493,6 +493,8 @@ const char *rs6000_type_string (tree type_node)
return "_Float128";
else if (type_node == float16_type_node)
return "_Float16";
+ else if (TARGET_BFLOAT16 && type_node == bfloat16_type_node)
+ return "__bfloat16";
else if (type_node == vector_pair_type_node)
return "__vector_pair";
else if (type_node == vector_quad_type_node)
@@ -758,6 +760,18 @@ rs6000_init_builtins (void)
else
ieee128_float_type_node = NULL_TREE;
+ /* __bfloat16 support. */
+ if (TARGET_BFLOAT16)
+ {
+ bfloat16_type_node = make_node (REAL_TYPE);
+ TYPE_PRECISION (bfloat16_type_node) = 16;
+ SET_TYPE_MODE (bfloat16_type_node, BFmode);
+ layout_type (bfloat16_type_node);
+ t = build_qualified_type (bfloat16_type_node, TYPE_QUAL_CONST);
+ lang_hooks.types.register_builtin_type (bfloat16_type_node,
+ "__bfloat16");
+ }
+
/* Vector pair and vector quad support. */
vector_pair_type_node = make_node (OPAQUE_TYPE);
SET_TYPE_MODE (vector_pair_type_node, OOmode);
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 5523a749f18b..798b6404f7e9 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -114,6 +114,7 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
+ | OPTION_MASK_BFLOAT16 \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
diff --git a/gcc/config/rs6000/rs6000-modes.def
b/gcc/config/rs6000/rs6000-modes.def
index 04dc1d8c9194..81de144a987f 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -48,6 +48,9 @@ FLOAT_MODE (IF, 16, ibm_extended_format);
/* Explicit IEEE 16-bit floating point. */
FLOAT_MODE (HF, 2, ieee_half_format);
+/* Explicit bfloat16 floating point. */
+FLOAT_MODE (BF, 2, arm_bfloat_half_format);
+
/* Add any extra modes needed to represent the condition code.
For the RS/6000, we need separate modes when unsigned (logical) comparisons
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 92511a8928b9..6eb53f3b4c8b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3925,6 +3925,14 @@ rs6000_option_override_internal (bool global_init_p)
error ("%qs requires at least %qs", "-mieee16", "-mcpu=power9");
}
+ /* -mbfloat16 needs power10 at a minimum. */
+ if (TARGET_BFLOAT16 && !TARGET_POWER10)
+ {
+ rs6000_isa_flags &= ~OPTION_MASK_BFLOAT16;
+ if (rs6000_isa_flags_explicit & OPTION_MASK_BFLOAT16)
+ error ("%qs requires at least %qs", "-mbfloat16", "-mcpu=power10");
+ }
+
/* If hard-float/altivec/vsx were explicitly turned off then don't allow
the -mcpu setting to enable options that conflict. */
if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
@@ -24541,6 +24549,7 @@ struct rs6000_opt_mask {
static struct rs6000_opt_mask const rs6000_opt_masks[] =
{
{ "altivec", OPTION_MASK_ALTIVEC, false, true },
+ { "bfloat16", OPTION_MASK_BFLOAT16, false,
true },
{ "block-ops-unaligned-vsx", OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX,
false, true },
{ "block-ops-vector-pair", OPTION_MASK_BLOCK_OPS_VECTOR_PAIR,
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 7b6cc75b3e38..3da282932395 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -552,6 +552,7 @@
(define_mode_iterator FMOVE128_GPR [TI
V16QI
V8HI
+ V8BF
V8HF
V4SI
V4SF
@@ -838,8 +839,8 @@
;; Reload iterator for creating the function to allocate a base register to
;; supplement addressing modes.
-(define_mode_iterator RELOAD [V16QI V8HI V8HF V4SI V2DI V4SF V2DF V1TI
- SF SD SI DF DD DI TI PTI KF IF TF HF
+(define_mode_iterator RELOAD [V16QI V8HI V8BF V8HF V4SI V2DI V4SF V2DF V1TI
+ SF SD SI DF DD DI TI PTI KF IF TF HF BF
OO XO])
;; Iterate over smin, smax
@@ -858,6 +859,10 @@
(SF "TARGET_P8_VECTOR")
(DI "TARGET_POWERPC64")])
+;; Mode iterator for 16-bit floating modes.
+(define_mode_iterator FP16 [(BF "TARGET_BFLOAT16")
+ (HF "TARGET_IEEE16")])
+
;; Mode iterator for floating point modes other than SF/DFmode that we
;; convert to/from _Float16 (HFmode) via DFmode.
(define_mode_iterator HF_CONVERT [TF KF IF SD DD TD])
@@ -8246,45 +8251,45 @@
p9v, *, *, *")])
-(define_expand "movhf"
- [(set (match_operand:HF 0 "nonimmediate_operand")
- (match_operand:HF 1 "any_operand"))]
- "TARGET_IEEE16"
+(define_expand "mov<mode>"
+ [(set (match_operand:FP16 0 "nonimmediate_operand")
+ (match_operand:FP16 1 "any_operand"))]
+ ""
{
if (MEM_P (operands[0]) && !REG_P (operands[1]))
- operands[1] = force_reg (HFmode, operands[1]);
+ operands[1] = force_reg (<MODE>mode, operands[1]);
})
-;; On power10, we can load up HFmode constants with xxspltiw or pli.
-(define_insn "*movhf_xxspltiw"
- [(set (match_operand:HF 0 "gpc_reg_operand" "=wa,r")
- (match_operand:HF 1 "ieee16_xxspltiw_constant" "eP,eP"))]
- "TARGET_IEEE16 && TARGET_POWER10 && TARGET_PREFIXED"
+;; On power10, we can load up HFmode and BFmode constants with xxspltiw
+;; or pli.
+(define_insn "*mov<mode>_xxspltiw"
+ [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r")
+ (match_operand:FP16 1 "ieee16_xxspltiw_constant" "eP,eP"))]
+ "TARGET_POWER10 && TARGET_PREFIXED"
{
rtx op1 = operands[1];
const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op1);
long real_words[VECTOR_128BIT_WORDS];
- real_to_target (real_words, rtype, HFmode);
+ real_to_target (real_words, rtype, <MODE>mode);
operands[2] = GEN_INT (real_words[0]);
- return (vsx_register_operand (operands[0], HFmode)
+ return (vsx_register_operand (operands[0], <MODE>mode)
? "xxspltiw %x0,%2"
: "li %0,%2");
}
[(set_attr "type" "vecperm,*")
(set_attr "prefixed" "yes")])
-(define_insn "*movhf_internal"
- [(set (match_operand:HF 0 "nonimmediate_operand"
+(define_insn "*mov<mode>_internal"
+ [(set (match_operand:FP16 0 "nonimmediate_operand"
"=wa, wa, Z, r, r,
m, r, wa, wa, r")
- (match_operand:HF 1 "any_operand"
+ (match_operand:FP16 1 "any_operand"
"wa, Z, wa, r, m,
r, wa, r, j, j"))]
- "TARGET_IEEE16
- && (gpc_reg_operand (operands[0], HFmode)
- || gpc_reg_operand (operands[1], HFmode))"
+ "gpc_reg_operand (operands[0], <MODE>mode)
+ || gpc_reg_operand (operands[1], <MODE>mode)"
"@
xxlor %x0,%x1,%x1
lxsihzx %x0,%y1
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 779c13d233b9..61fecea0e049 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -650,6 +650,10 @@ mieee16-gpr-args
Target Undocumented Var(TARGET_IEEE16_GPR_ARGS) Init(1) Save
Pass _Float16 in GPR registers.
+mbfloat16
+Target Undocumented Mask(BFLOAT16) Var(rs6000_isa_flags)
+Enable or disable __bfloat16 support.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index ed427ea05e9b..0a9f092c1951 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -52,6 +52,7 @@
;; Vector logical modes
(define_mode_iterator VEC_L [V16QI
V8HI
+ V8BF
V8HF
V4SI
V2DI
@@ -68,6 +69,7 @@
V8HI
V4SI
V2DI
+ V8BF
V8HF
V4SF
V2DF
@@ -85,6 +87,7 @@
V8HI
V4SI
V2DI
+ V8BF
V8HF
V4SF
V2DF])
@@ -100,6 +103,7 @@
(V8HI "HI")
(V4SI "SI")
(V2DI "DI")
+ (V8BF "BF")
(V8HF "HF")
(V4SF "SF")
(V2DF "DF")
@@ -111,6 +115,7 @@
(V8HI "hi")
(V4SI "si")
(V2DI "di")
+ (V8BF "bf")
(V8HF "hf")
(V4SF "sf")
(V2DF "df")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 09b4d53813ba..aee4a9ba8c1a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -47,12 +47,14 @@
(define_mode_iterator VSX_F [V4SF V2DF])
;; Iterator for 8 element vectors
-(define_mode_iterator V8HI_V8HF [V8HI
- (V8HF "TARGET_IEEE16")])
+(define_mode_iterator VECTOR_16BIT [V8HI
+ (V8BF "TARGET_BFLOAT16")
+ (V8HF "TARGET_IEEE16")])
;; Iterator for logical types supported by VSX
(define_mode_iterator VSX_L [V16QI
V8HI
+ (V8BF "TARGET_BFLOAT16")
(V8HF "TARGET_IEEE16")
V4SI
V2DI
@@ -66,6 +68,7 @@
;; Iterator for memory moves.
(define_mode_iterator VSX_M [V16QI
V8HI
+ (V8BF "TARGET_BFLOAT16")
(V8HF "TARGET_IEEE16")
V4SI
V2DI
@@ -77,6 +80,7 @@
TI])
(define_mode_attr VSX_XXBR [(V8HI "h")
+ (V8BF "h")
(V8HF "h")
(V4SI "w")
(V4SF "w")
@@ -87,6 +91,7 @@
;; Map into the appropriate load/store name based on the type
(define_mode_attr VSm [(V16QI "vw4")
(V8HI "vw4")
+ (V8BF "vw4")
(V8HF "vw4")
(V4SI "vw4")
(V4SF "vw4")
@@ -101,6 +106,7 @@
;; Map the register class used
(define_mode_attr VSr [(V16QI "v")
(V8HI "v")
+ (V8BF "v")
(V8HF "v")
(V4SI "v")
(V4SF "wa")
@@ -117,6 +123,7 @@
;; What value we need in the "isa" field, to make the IEEE QP float work.
(define_mode_attr VSisa [(V16QI "*")
(V8HI "*")
+ (V8BF "p10")
(V8HF "p9v")
(V4SI "*")
(V4SF "*")
@@ -134,6 +141,7 @@
;; integer modes.
(define_mode_attr ??r [(V16QI "??r")
(V8HI "??r")
+ (V8BF "??r")
(V8HF "??r")
(V4SI "??r")
(V4SF "??r")
@@ -147,6 +155,7 @@
;; A mode attribute used for 128-bit constant values.
(define_mode_attr nW [(V16QI "W")
(V8HI "W")
+ (V8BF "W")
(V8HF "W")
(V4SI "W")
(V4SF "W")
@@ -175,6 +184,7 @@
;; operation
(define_mode_attr VSv [(V16QI "v")
(V8HI "v")
+ (V8BF "v")
(V8HF "v")
(V4SI "v")
(V4SF "v")
@@ -409,6 +419,7 @@
;; Like VM2 in altivec.md, just do char, short, int, long, float and double
(define_mode_iterator VM3 [V4SI
V8HI
+ V8BF
V8HF
V16QI
V4SF
@@ -421,6 +432,7 @@
(define_mode_attr VM3_char [(V2DI "d")
(V4SI "w")
(V8HI "h")
+ (V8BF "h")
(V8HF "h")
(V16QI "b")
(V2DF "d")
@@ -557,20 +569,20 @@
(set_attr "length" "8")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
- [(set (match_operand:V8HI_V8HF 0 "vsx_register_operand" "=wa")
- (match_operand:V8HI_V8HF 1 "indexed_or_indirect_operand" "Z"))]
+ [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa")
+ (match_operand:VECTOR_16BIT 1 "indexed_or_indirect_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"#"
"&& 1"
[(set (match_dup 2)
- (vec_select:V8HI_V8HF
+ (vec_select:VECTOR_16BIT
(match_dup 1)
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))
(set (match_dup 0)
- (vec_select:V8HI_V8HF
+ (vec_select:VECTOR_16BIT
(match_dup 2)
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
@@ -818,26 +830,26 @@
"")
(define_insn "*vsx_le_perm_store_<mode>"
- [(set (match_operand:V8HI_V8HF 0 "indexed_or_indirect_operand" "=Z")
- (match_operand:V8HI_V8HF 1 "vsx_register_operand" "wa"))]
+ [(set (match_operand:VECTOR_16BIT 0 "indexed_or_indirect_operand" "=Z")
+ (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR"
"#"
[(set_attr "type" "vecstore")
(set_attr "length" "12")])
(define_split
- [(set (match_operand:V8HI_V8HF 0 "indexed_or_indirect_operand")
- (match_operand:V8HI_V8HF 1 "vsx_register_operand"))]
+ [(set (match_operand:VECTOR_16BIT 0 "indexed_or_indirect_operand")
+ (match_operand:VECTOR_16BIT 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
- (vec_select:V8HI_V8HF
+ (vec_select:VECTOR_16BIT
(match_dup 1)
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))
(set (match_dup 0)
- (vec_select:V8HI_V8HF
+ (vec_select:VECTOR_16BIT
(match_dup 2)
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
@@ -876,25 +888,25 @@
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
- [(set (match_operand:V8HI_V8HF 0 "indexed_or_indirect_operand")
- (match_operand:V8HI_V8HF 1 "vsx_register_operand"))]
+ [(set (match_operand:VECTOR_16BIT 0 "indexed_or_indirect_operand")
+ (match_operand:VECTOR_16BIT 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
- (vec_select:V8HI_V8HF
+ (vec_select:VECTOR_16BIT
(match_dup 1)
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))
(set (match_dup 0)
- (vec_select:V8HI_V8HF
+ (vec_select:VECTOR_16BIT
(match_dup 1)
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))
(set (match_dup 1)
- (vec_select:V8HI_V8HF
+ (vec_select:VECTOR_16BIT
(match_dup 1)
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
@@ -1450,9 +1462,9 @@
[(set_attr "type" "vecload")])
(define_expand "vsx_ld_elemrev_<mode>"
- [(set (match_operand:V8HI_V8HF 0 "vsx_register_operand" "=wa")
- (vec_select:V8HI_V8HF
- (match_operand:V8HI_V8HF 1 "memory_operand" "Z")
+ [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa")
+ (vec_select:VECTOR_16BIT
+ (match_operand:VECTOR_16BIT 1 "memory_operand" "Z")
(parallel [(const_int 7) (const_int 6)
(const_int 5) (const_int 4)
(const_int 3) (const_int 2)
@@ -1484,9 +1496,9 @@
})
(define_insn "*vsx_ld_elemrev_<mode>_internal"
- [(set (match_operand:V8HI_V8HF 0 "vsx_register_operand" "=wa")
- (vec_select:V8HI_V8HF
- (match_operand:V8HI_V8HF 1 "memory_operand" "Z")
+ [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa")
+ (vec_select:VECTOR_16BIT
+ (match_operand:VECTOR_16BIT 1 "memory_operand" "Z")
(parallel [(const_int 7) (const_int 6)
(const_int 5) (const_int 4)
(const_int 3) (const_int 2)
@@ -1600,9 +1612,9 @@
[(set_attr "type" "vecstore")])
(define_expand "vsx_st_elemrev_<mode>"
- [(set (match_operand:V8HI_V8HF 0 "memory_operand" "=Z")
- (vec_select:V8HI_V8HF
- (match_operand:V8HI_V8HF 1 "vsx_register_operand" "wa")
+ [(set (match_operand:VECTOR_16BIT 0 "memory_operand" "=Z")
+ (vec_select:VECTOR_16BIT
+ (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa")
(parallel [(const_int 7) (const_int 6)
(const_int 5) (const_int 4)
(const_int 3) (const_int 2)
@@ -1642,9 +1654,9 @@
[(set_attr "type" "vecstore")])
(define_insn "*vsx_st_elemrev_<mode>_internal"
- [(set (match_operand:V8HI_V8HF 0 "memory_operand" "=Z")
- (vec_select:V8HI_V8HF
- (match_operand:V8HI_V8HF 1 "vsx_register_operand" "wa")
+ [(set (match_operand:VECTOR_16BIT 0 "memory_operand" "=Z")
+ (vec_select:VECTOR_16BIT
+ (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa")
(parallel [(const_int 7) (const_int 6)
(const_int 5) (const_int 4)
(const_int 3) (const_int 2)
@@ -3335,9 +3347,9 @@
[(set_attr "type" "vecperm")])
(define_insn "xxswapd_<mode>"
- [(set (match_operand:V8HI_V8HF 0 "vsx_register_operand" "=wa")
- (vec_select:V8HI_V8HF
- (match_operand:V8HI_V8HF 1 "vsx_register_operand" "wa")
+ [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa")
+ (vec_select:VECTOR_16BIT
+ (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
@@ -3438,9 +3450,9 @@
[(set_attr "type" "vecload")])
(define_insn "*vsx_lxvd2x8_le_<MODE>"
- [(set (match_operand:V8HI_V8HF 0 "vsx_register_operand" "=wa")
- (vec_select:V8HI_V8HF
- (match_operand:V8HI_V8HF 1 "memory_operand" "Z")
+ [(set (match_operand:VECTOR_16BIT 0 "vsx_register_operand" "=wa")
+ (vec_select:VECTOR_16BIT
+ (match_operand:VECTOR_16BIT 1 "memory_operand" "Z")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
@@ -3514,9 +3526,9 @@
(set_attr "length" "8")])
(define_insn "*vsx_stxvd2x8_le_<MODE>"
- [(set (match_operand:V8HI_V8HF 0 "memory_operand" "=Z")
- (vec_select:V8HI_V8HF
- (match_operand:V8HI_V8HF 1 "vsx_register_operand" "wa")
+ [(set (match_operand:VECTOR_16BIT 0 "memory_operand" "=Z")
+ (vec_select:VECTOR_16BIT
+ (match_operand:VECTOR_16BIT 1 "vsx_register_operand" "wa")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)
(const_int 0) (const_int 1)
@@ -4095,7 +4107,8 @@
if (which_alternative == 0
&& ((<MODE>mode == V16QImode
&& INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 7 : 8))
- || ((<MODE>mode == V8HImode || <MODE>mode == V8HFmode)
+ || ((<MODE>mode == V8HImode || <MODE>mode == V8HFmode
+ || <MODE>mode == V8BFmode)
&& INTVAL (operands[2]) == (BYTES_BIG_ENDIAN ? 3 : 4))))
{
enum machine_mode dest_mode = GET_MODE (operands[0]);
@@ -4174,7 +4187,8 @@
else
vec_tmp = src;
}
- else if (<MODE>mode == V8HImode || <MODE>mode == V8HFmode)
+ else if (<MODE>mode == V8HImode || <MODE>mode == V8HFmode
+ || <MODE>mode == V8BFmode)
{
if (value != 3)
emit_insn (gen_altivec_vsplth_direct (vec_tmp, src, element));
