https://gcc.gnu.org/g:f731fa580156d07f6347cb87931ce7b9cf2acbb4
commit r16-4112-gf731fa580156d07f6347cb87931ce7b9cf2acbb4 Author: Jie Mei <[email protected]> Date: Fri Jan 17 16:51:45 2025 +0800 MIPS: Add conditions for use of the -mmips16e2 and -mips16 option. Changes from V1: * Raise the minimal revision to r2. MIPS16e2 ASE is a superset of MIPS16e ASE, which is again a superset of MIPS16 ASE. Later, all of them are forbidden in Release 6. Make -mmips16e2 imply -mips16 as the ASE requires, so users won't be surprised even if they expect it to. Meanwhile, check if mips_isa_rev <= 5 when -mips16 is effective and >= 2 when -mmips16e2 is effective. Co-developed-by: Rong Zhang <[email protected]> Signed-off-by: Rong Zhang <[email protected]> gcc/ChangeLog: * config/mips/mips.cc(mips_option_override):Add conditions for use of the -mmips16e2 and -mips16 option. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2-cache.c: Use isa_rev>=2 instead of -mips32r2 and remove -mips16 option. * gcc.target/mips/mips16e2-cmov.c: Add isa_rev>=2 and remove -mips16 option. * gcc.target/mips/mips16e2-gp.c: Same as above. * gcc.target/mips/mips16e2.c: Same as above. Diff: --- gcc/config/mips/mips.cc | 19 +++++++++++++++++++ gcc/testsuite/gcc.target/mips/mips16e2-cache.c | 2 +- gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 2 +- gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 2 +- gcc/testsuite/gcc.target/mips/mips16e2.c | 2 +- 5 files changed, 23 insertions(+), 4 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 81eaa3cfb2ad..fa9ac079a01d 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -20419,6 +20419,16 @@ mips_option_override (void) if (TARGET_MICROMIPS && TARGET_MIPS16) error ("unsupported combination: %s", "-mips16 -mmicromips"); + /* Make -mmips16e2 imply -mips16 and forbid its coexistence with + -mmicromips as the ASE requires. */ + if (TARGET_MIPS16E2) + { + if (TARGET_MICROMIPS) + error ("unsupported combination: %s", "-mmips16e2 -mmicromips"); + + target_flags |= MASK_MIPS16; + } + /* Prohibit Paired-Single and MSA combination. This is software restriction rather than architectural. */ if (ISA_HAS_MSA && TARGET_PAIRED_SINGLE_FLOAT) @@ -20671,6 +20681,15 @@ mips_option_override (void) "-mcompact-branches=never"); } + /* MIPS16* ASE is forbidden in Release 6, so -mips16 is not available + for MIPS R6 onwards. */ + if ((mips_base_compression_flags & MASK_MIPS16) && mips_isa_rev >= 6) + error ("MIPS16* ASE is forbidden in Release 6"); + + /* Make sure that the user use Release[2,5] when using -mmips16e2. */ + if (TARGET_MIPS16E2 && mips_isa_rev < 2) + error ("%<-mmips16e2%> requires Release[2,5]"); + /* Require explicit relocs for MIPS R6 onwards. This enables simplification of the compact branch and jump support through the backend. */ if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c index dcc39b580f52..8caacb17d7a9 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips32r2 -mips16 -mmips16e2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */ /* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ /* Test cache. */ diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c index 129ea23b65b1..a8a28a4d8600 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2 -mbranch-cost=2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2 -mbranch-cost=2" } */ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ /* Test MOVN. */ diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c index 7955472bde30..70d6230f017f 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */ /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */ /* Generate GP-relative ADDIU. */ diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c index 166aa7422687..1b4b840bb404 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */ /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */ /* ANDI is a two operand instruction. Hence, it won't be generated if src and
