https://gcc.gnu.org/g:10bb371eee6357cd32ffc8cfddcd62bd8b182c4b
commit r16-4117-g10bb371eee6357cd32ffc8cfddcd62bd8b182c4b Author: YunQiang Su <[email protected]> Date: Sat Sep 27 22:24:49 2025 +0800 MIPS/testsuite: Use isa_rev=2 instead of >=2 So that they won't fail for r6 targets. gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: Use isa_rev=2 instead of >=2. * gcc.target/mips/mips16e2-cache.c: Ditto. * gcc.target/mips/mips16e2-cmov.c: Ditto. * gcc.target/mips/mips16e2-gp.c: Ditto. Diff: --- gcc/testsuite/gcc.target/mips/mips16e2-cache.c | 2 +- gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 2 +- gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 2 +- gcc/testsuite/gcc.target/mips/mips16e2.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c index 8caacb17d7a9..c79157589992 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */ /* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */ /* Test cache. */ diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c index a8a28a4d8600..8d71e88596cc 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2 -mbranch-cost=2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2 -mbranch-cost=2" } */ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ /* Test MOVN. */ diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c index 70d6230f017f..5fab454d5e06 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */ /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */ /* Generate GP-relative ADDIU. */ diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c index 1b4b840bb404..33c4bb52ccca 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -1,4 +1,4 @@ -/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=2 -mmips16e2" } */ +/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev=2 -mmips16e2" } */ /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */ /* ANDI is a two operand instruction. Hence, it won't be generated if src and
