https://gcc.gnu.org/g:96fc9d642fe9a0fd0901c9686aaeb128b0768951
commit 96fc9d642fe9a0fd0901c9686aaeb128b0768951 Author: Michael Meissner <[email protected]> Date: Wed Oct 1 13:05:22 2025 -0400 Use xxsldwi instead of xxspltw for bfloat16. 2025-10-01 Michael Meissner <[email protected]> gcc/ * config/rs6000/altivec.md (altivec_vsplth_v8bf): Delete insn. * config/rs6000/rs6000.md (UNSPEC_V8BF_SHIFT_LEFT_32BIT): New unspec. (extendbf<mode>2): Use xxsldwi to get the bfloat16 into upper 32 bits. (v8bf_shift_left_32bit): New insn. Diff: --- gcc/config/rs6000/altivec.md | 20 -------------------- gcc/config/rs6000/rs6000.md | 15 +++++++++++++-- 2 files changed, 13 insertions(+), 22 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index f50da15b08dc..fb960f7ba966 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2478,26 +2478,6 @@ } [(set_attr "type" "vecperm")]) -;; Splat instruction needed to allow conversion of __bfloat16 -;; (i.e. BFmode) to SFmode/DFmode. -;; (define_insn "altivec_vsplth_v8bf" -;; [(set (match_operand:V8BF 0 "register_operand" "=v") -;; (unspec:V8BF [(match_operand:BF 1 "register_operand" "v") -;; (match_operand:QI 2 "const_0_to_7_operand" "i")] -;; UNSPEC_VSPLT_DIRECT))] -;; "TARGET_BFLOAT16" -;; "vsplth %0,%1,%2" -;; [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsplth_v8bf" - [(set (match_operand:V8BF 0 "register_operand" "=wa") - (unspec:V8BF [(match_operand:BF 1 "register_operand" "wa") - (match_operand:QI 2 "const_0_to_7_operand" "i")] - UNSPEC_VSPLT_DIRECT))] - "TARGET_BFLOAT16" - "xxspltw %x0,%x1,1" - [(set_attr "type" "vecperm")]) - (define_insn "altivec_vspltis<VI_char>" [(set (match_operand:VI 0 "register_operand" "=v") (vec_duplicate:VI diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5486d9489e18..86687187137a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -173,6 +173,7 @@ UNSPEC_XXSPLTIW_CONST UNSPEC_FMAX UNSPEC_FMIN + UNSPEC_V8BF_SHIFT_LEFT_32BIT ]) ;; @@ -5907,8 +5908,8 @@ rtx op2_v4sf = gen_lowpart (V4SFmode, op2_v8bf); - /* VSPLTH -- duplicate BFmode into all elements. */ - emit_insn (gen_altivec_vsplth_v8bf (op2_v8bf, op1, GEN_INT (3))); + /* XXSLDWI -- shift BFmode element into the upper 32 bits. */ + emit_insn (gen_v8bf_shift_left_32bit (op2_v8bf, op1)); /* XVCVBF16SPN -- convert even V8BFmode elements to V4SFmode. */ emit_insn (gen_vsx_xvcvbf16spn_v8bf (op2_v4sf, op2_v8bf)); @@ -5923,6 +5924,16 @@ [(set_attr "type" "fpsimple") (set_attr "length" "12")]) +;; Vector shift left by 32 bits to get the bfloat16 value into the +;; upper 32 bits for the conversion. +(define_insn "v8bf_shift_left_32bit" + [(set (match_operand:V8BF 0 "register_operand" "=wa") + (unspec:V8BF [(match_operand:BF 1 "register_operand" "wa")] + UNSPEC_V8BF_SHIFT_LEFT_32BIT))] + "TARGET_BFLOAT16" + "xxsldwi %x0,%x1,%x1,1" + [(set_attr "type" "vecperm")]) + ;; Convert SFmode/DFmode to BFmode. ;; 2 instructions are generated: ;; XSCVDPSPN -- convert SFmode/DFmode scalar to V4SFmode
