https://gcc.gnu.org/g:f69be51e4667fedc57927bc2000968bb5906520f
commit f69be51e4667fedc57927bc2000968bb5906520f Author: Michael Meissner <[email protected]> Date: Fri Oct 17 04:23:33 2025 -0400 Revert changes Diff: --- gcc/ChangeLog.float | 13 +------------ gcc/config/rs6000/float16.md | 8 ++++---- 2 files changed, 5 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog.float b/gcc/ChangeLog.float index 48c3b7a7e9de..81dc56c56a3a 100644 --- a/gcc/ChangeLog.float +++ b/gcc/ChangeLog.float @@ -1,15 +1,4 @@ -==================== Branch work222-float, patch #337 ==================== - -Fix 16-bit floating point ordering. - -2025-10-17 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/ffloat16.md (vec_unpacks_hi_v8hf): Fix ordering issue. - (vec_unpacks_lo_v8hf): Likewise. - (vec_unpacks_hi_v8bf): Likewise. - (vec_unpacks_lo_v8bf): Likewise. +==================== Branch work222-float, patch #337 was reverted ==================== ==================== Branch work222-float, patch #336 ==================== diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index c868dbc1ad93..1ea070c4486e 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -1013,7 +1013,7 @@ { rtx reg = gen_reg_rtx (V8HFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); DONE; }) @@ -1025,7 +1025,7 @@ { rtx reg = gen_reg_rtx (V8HFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); DONE; }) @@ -1047,7 +1047,7 @@ { rtx reg = gen_reg_rtx (V8BFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); DONE; }) @@ -1059,7 +1059,7 @@ { rtx reg = gen_reg_rtx (V8BFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); DONE; })
