https://gcc.gnu.org/g:188e8eb838f9693696a890c08f184a634b86c6a7
commit 188e8eb838f9693696a890c08f184a634b86c6a7 Author: Michael Meissner <[email protected]> Date: Tue Oct 14 01:59:40 2025 -0400 Add patterns for v8hf vectorization. 2025-10-13 Michael Meissner <[email protected]> gcc/ * config/rs6000/altivec.md (altivec_vsplth_internal_v8h): New insn. (altivec_lvehf): Likewise. Diff: --- gcc/config/rs6000/altivec.md | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index fb960f7ba966..5454e2453bb2 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2402,6 +2402,22 @@ } [(set_attr "type" "vecperm")]) + +(define_insn "*altivec_vsplth_internal_v8hx" + [(set (match_operand:V8HF 0 "register_operand" "=v") + (vec_duplicate:V8HF + (vec_select:HF (match_operand:V8HF 1 "register_operand" "v") + (parallel + [(match_operand:QI 2 "const_0_to_7_operand" "")]))))] + "TARGET_ALTIVEC" +{ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (7 - INTVAL (operands[2])); + + return "vsplth %0,%1,%2"; +} + [(set_attr "type" "vecperm")]) + (define_insn "altivec_vsplth_direct" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") @@ -3130,6 +3146,15 @@ "lvewx %0,%y1" [(set_attr "type" "vecload")]) +(define_insn "*altivec_lvehf" + [(parallel + [(set (match_operand:V8HF 0 "register_operand" "=v") + (match_operand:V8HF 1 "memory_operand" "Z")) + (unspec [(const_int 0)] UNSPEC_LVE)])] + "TARGET_ALTIVEC" + "lvehx %0,%y1" + [(set_attr "type" "vecload")]) + (define_insn "altivec_lvxl_<mode>" [(parallel [(set (match_operand:VM2 0 "register_operand" "=v")
