https://gcc.gnu.org/g:71ed857dbdbf3c719cb3c6357d83da0e14c4d32b
commit 71ed857dbdbf3c719cb3c6357d83da0e14c4d32b Author: Michael Meissner <[email protected]> Date: Tue Oct 21 00:10:05 2025 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.float | 120 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/gcc/ChangeLog.float b/gcc/ChangeLog.float index 1e2e79e3bf11..640e4c4e5fe4 100644 --- a/gcc/ChangeLog.float +++ b/gcc/ChangeLog.float @@ -1,3 +1,123 @@ +==================== Branch work223-float, patch #300 ==================== + + +Add _Float16 and __bfloat16 support. + +2025-10-20 Michael Meissner <[email protected]> + +gcc/ + + * config.gcc (powerpc*-*-*): Add build of float16.o. + * config/rs6000/altivec.md (VM): Add 16-bit floating point support. + (VM2): Likewise. + (VI_char): Likewise. + (VI_scalar): Likewise. + (VI_unit): Likewise. + (VP_small): Likewise. + (VP_small_lc): Likewise. + (VU_char): Likewise. + * config/rs6000/float16.cc: New file. + * config/rs6000/float16.md: Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Add 16-bit + floating point support. + * config/rs6000/rs6000-call.cc (USE_FP_FOR_ARG_P): Likewise. + (init_cumulative_args): Likewise. + (rs6000_function_arg): Likewise. + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add comment for + adding -mfloat16 in the future. + (OTHER_POWER10_MASKS): Add comment for adding -mbfloat16 in the future. + (POWERPC_MASKS): Add -mbfloat16 and -mfloat16. + * config/rs6000/rs6000-modes.def (HFmode): New mode for 16-bit floating + point. + (BRmode): Likewise. + (V4HFmode): Likewise. + (V4BFmode): Likewise. + * config/rs6000/rs6000-p8swap.cc (rs6000_gen_stvx): Remove V8HFmode. + (rs6000_gen_lvx): Likewise. + (replace_swapped_load_constant): Likewise. + * config/rs6000/rs6000-protos.h (vec_const_128bit_type): Add mode field. + (fp16_operation): New enumeration. + (bfloat16_operation_as_v4sf): New declaration. + (fp16_vectorization): Likewise. + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add + support for 16-bit floating point. + (rs6000_modes_tieable_p): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_option_override_internal): Likewise. + (xxspltib_constant_p): Likewise. + (xxspltib_constant_p): Likewise. + (output_vec_const_move): Likewise. + (rs6000_expand_vector_init): Likewise. + (reg_offset_addressing_ok_p): Likewise. + (rs6000_legitimate_offset_address_p): Likewise. + (legitimate_lo_sum_address_p): Likewise. + (rs6000_const_vec): Likewise. + (rs6000_emit_move): Likewise. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_can_change_mode_class): Likewise. + (rs6000_load_constant_and_splat): Likewise. + (rs6000_function_value): Likewise. + (rs6000_scalar_mode_supported_p): Likewise. + (rs6000_floatn_mode): Likewise. + (s6000_opt_masks): Likewise. + (constant_fp_to_128bit_vector): Likewise. + (vec_const_128bit_to_bytes): Likewise. + (constant_generates_xxspltiw): Likewise. + * config/rs6000/rs6000.h (TARGET_BFLOAT16_HW): Likewise. + (TARGET_FLOAT16_HW): Likewise. + (FP16_SCALAR_MODE_P): Likewise. + (FP16_HW_SCALAR_MODE_P): Likewise. + (FP16_VECTOR_MODE_P): Likewise. + (ALTIVEC_VECTOR_MODE): Likewise. + * config/rs6000/rs6000.md (FMOVE128_GPR): Likewise. + (wd): Likewise. + (du_or_d): Likewise. + (BOOL_128): Likewise. + (BOOL_REGS_OUTPUT): Likewise. + (BOOL_REGS_OP1): Likewise. + (BOOL_REGS_OP2): Likewise. + (BOOL_REGS_UNARY): Likewise. + (RELOAD): Likewise. + (float16.md): Include new file. + * config/rs6000/rs6000.opt (-mbfloat16): New switch. + (-mfloat16-gpr-args): Likewise. + (-mbfloat16): Likewise. + * config/rs6000/t-rs6000 (float16.o): Add 16-bit floating point support. + * config/rs6000/vector.md (VEC_L): Likewise. + (VEC_M): Likewise. + (VEC_E): Likewise. + (VEC_base): Likewise. + (VEC_base_l): Likewise. + * config/rs6000/vsx.md (VECTOR_16BIT): Likewise. + (VSX_M): Likewise. + (VSX_XXBR): Likewise. + (VSm): Likewise. + (VSr): Likewise. + (VSisa): Likewise. + (??r): Likewise. + (nW): Likewise. + (VSv): Likewise. + (VM3): Likewise. + (VM3_char): Likewise. + (vsx_le_perm_load_<mode>): Likewise. + (vsx_le_perm_store_<mode>): Likewise. + (p8 permute splitter): Likewise. + (vsx_ld_elemrev_v8hi): Likewise. + (vsx_ld_elemrev_<mode>_internal): Likewise. + (vsx_st_elemrev_<mode>): Likewise. + (vsx_st_elemrev_v8hi): Likewise. + (sx_st_elemrev_<mode>_internal): Likewise. + (sx_xscvspdpn_sf): Likewise. + (xxswapd_<mode>): Likewise. + (vsx_lxvd2x8_le_<MODE): Likewise. + (vsx_stxvd2x8_le_<MODE>): Likewise. + (vsx_extract_<mode>_di_p9): Likewise. + (vsx_extract_<mode>_store_p9): Likewise. + (vsx_extract_v4si_w023): Likewise. + ==================== Branch work223-float, baseline ==================== 2025-10-20 Michael Meissner <[email protected]>
