https://gcc.gnu.org/g:c798ab356082d532ba9945d07f02e30447e03892
commit c798ab356082d532ba9945d07f02e30447e03892 Author: Pan Li <[email protected]> Date: Mon Jul 21 09:06:52 2025 +0800 RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode This patch would like to combine the vec_duplicate + vaaddu.vv to the vaaddu.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the GR2VR cost is greater than zero. Assume we have example code like below, GR2VR cost is 0. #define DEF_AVG_FLOOR(NT, WT) \ NT \ test_##NT##_avg_floor(NT x, NT y) \ { \ return (NT)(((WT)x + (WT)y) >> 1); \ } #define AVG_FLOOR_FUNC(T) test_##T##_avg_floor DEF_AVG_FLOOR(uint32_t, uint64_t) DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC(T), sat_add) Before this patch: 11 │ beq a3,zero,.L8 12 │ vsetvli a5,zero,e32,m1,ta,ma 13 │ vmv.v.x v2,a2 14 │ slli a3,a3,32 15 │ srli a3,a3,32 16 │ .L3: 17 │ vsetvli a5,a3,e32,m1,ta,ma 18 │ vle32.v v1,0(a1) 19 │ slli a4,a5,2 20 │ sub a3,a3,a5 21 │ add a1,a1,a4 22 │ vaaddu.vv v1,v1,v2 23 │ vse32.v v1,0(a0) 24 │ add a0,a0,a4 25 │ bne a3,zero,.L3 After this patch: 11 │ beq a3,zero,.L8 12 │ slli a3,a3,32 13 │ srli a3,a3,32 14 │ .L3: 15 │ vsetvli a5,a3,e32,m1,ta,ma 16 │ vle32.v v1,0(a1) 17 │ slli a4,a5,2 18 │ sub a3,a3,a5 19 │ add a1,a1,a4 20 │ vaaddu.vx v1,v1,a2 21 │ vse32.v v1,0(a0) 22 │ add a0,a0,a4 23 │ bne a3,zero,.L3 gcc/ChangeLog: * config/riscv/autovec-opt.md (*uavg_floor_vx_<mode>): Add pattern for vaaddu.vx combine. * config/riscv/riscv.cc (get_vector_binary_rtx_cost): Add UNSPEC handling for UNSPEC_VAADDU. (riscv_rtx_costs): Ditto. Signed-off-by: Pan Li <[email protected]> (cherry picked from commit 9e2aaaba47cf635169e9051c4e86f39d04c69f1d) Diff: --- gcc/config/riscv/autovec-opt.md | 62 +++++++++++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 29 +++++++++++++++++-- 2 files changed, 89 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 12217c03304b..d88494227913 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1714,6 +1714,68 @@ } [(set_attr "type" "vialu")]) +(define_insn_and_split "*uavg_floor_vx_<mode>" + [(set (match_operand:V_VLSI 0 "register_operand") + (if_then_else:V_VLSI + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) + (unspec:V_VLSI + [(match_operand:V_VLSI 3 "register_operand") + (vec_duplicate:V_VLSI + (match_operand:<VEL> 4 "register_operand"))] UNSPEC_VAADDU) + (unspec:V_VLSI + [(match_operand:DI 2 "register_operand")] UNSPEC_VUNDEF)))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code code = code_for_pred_scalar (UNSPEC_VAADDU, <MODE>mode); + rtx ops[] = {operands[0], operands[3], operands[4]}; + riscv_vector::emit_vlmax_insn (code, riscv_vector::BINARY_OP_VXRM_RDN, ops); + DONE; + } + [(set_attr "type" "vaalu")]) + +(define_insn_and_split "*uavg_floor_vx_<mode>" + [(set (match_operand:V_VLSI 0 "register_operand") + (if_then_else:V_VLSI + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand") + (match_operand 5 "vector_length_operand") + (match_operand 6 "const_int_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE) + (unspec:V_VLSI + [(vec_duplicate:V_VLSI + (match_operand:<VEL> 4 "register_operand")) + (match_operand:V_VLSI 3 "register_operand")] UNSPEC_VAADDU) + (unspec:V_VLSI + [(match_operand:DI 2 "register_operand")] UNSPEC_VUNDEF)))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code code = code_for_pred_scalar (UNSPEC_VAADDU, <MODE>mode); + rtx ops[] = {operands[0], operands[3], operands[4]}; + riscv_vector::emit_vlmax_insn (code, riscv_vector::BINARY_OP_VXRM_RDN, ops); + DONE; + } + [(set_attr "type" "vaalu")]) + ;; ============================================================================= ;; Combine vec_duplicate + op.vv to op.vf ;; Include diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 261f171df1cc..860f930a2d13 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3968,9 +3968,20 @@ get_vector_binary_rtx_cost (rtx x, int scalar2vr_cost) { gcc_assert (riscv_v_ext_mode_p (GET_MODE (x))); - rtx op_0 = XEXP (x, 0); - rtx op_1 = XEXP (x, 1); rtx neg; + rtx op_0; + rtx op_1; + + if (GET_CODE (x) == UNSPEC) + { + op_0 = XVECEXP (x, 0, 0); + op_1 = XVECEXP (x, 0, 1); + } + else + { + op_0 = XEXP (x, 0); + op_1 = XEXP (x, 1); + } if (GET_CODE (op_0) == VEC_DUPLICATE || GET_CODE (op_1) == VEC_DUPLICATE) @@ -4025,6 +4036,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN case SS_MINUS: *total = get_vector_binary_rtx_cost (op, scalar2vr_cost); break; + case UNSPEC: + { + switch (XINT (op, 1)) + { + case UNSPEC_VAADDU: + *total + = get_vector_binary_rtx_cost (op, scalar2vr_cost); + break; + default: + *total = COSTS_N_INSNS (1); + break; + } + } + break; default: *total = COSTS_N_INSNS (1); break;
