https://gcc.gnu.org/g:94e605a8080e01c0eb575c22310ab7caadc58f86
commit r16-5074-g94e605a8080e01c0eb575c22310ab7caadc58f86 Author: Pan Li <[email protected]> Date: Sun Oct 26 15:21:15 2025 +0800 RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmaccu.vx on GR2VR cost This patch would like to combine the vec_duplicate + vwmaccu.wv to the vwmaccu.vx. From example as below code. The related pattern will depend on the cost of vec_duplicate from GR2VR. Then the late-combine will take action if the cost of GR2VR is zero, and reject the combination if the GR2VR cost is greater than zero. Assume we have asm code like below, GR2VR cost is 0. Before this patch: 11 beq a3,zero,.L8 12 vsetvli a5,zero,e32,m1,ta,ma 13 vmv.v.x v2,a2 ... 16 .L3: 17 vsetvli a5,a3,e32,m1,ta,ma ... 22 vwmaccu.wv v1,v2,v3 ... 25 bne a3,zero,.L3 After this patch: 11 beq a3,zero,.L8 ... 14 .L3: 15 vsetvli a5,a3,e32,m1,ta,ma ... 20 vwmaccu.wx v1,a2,v3 ... 23 bne a3,zero,.L3 Unfortunately, and similar as vwaddu.vv, only widening from uint32_t to uint64_t has the necessary zero-extend during combine, we loss the extend op after expand for any other types. gcc/ChangeLog: * config/riscv/autovec-opt.md (*widen_mul_plus_vx_<mode>): Add new pattern to combine the vwmaccu.vx. * config/riscv/vector.md (*pred_widen_mul_plus_u_vx<mode>_undef): Add undef define_insn for vmwaccu.vx emiting. (@pred_widen_mul_plus_u_vx<mode>): Ditto. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/autovec-opt.md | 25 +++++++++++++++++++++ gcc/config/riscv/vector.md | 50 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index d2705cf0fb92..063c9a0122b6 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -1951,6 +1951,31 @@ } [(set_attr "type" "viwalu")]) +(define_insn_and_split "*widen_mul_plus_vx_<mode>" + [(set (match_operand:VWEXTI 0 "register_operand") + (plus:VWEXTI + (mult:VWEXTI + (zero_extend:VWEXTI + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")) + (vec_duplicate:VWEXTI + (zero_extend:<VEL> + (match_operand:<VSUBEL> 1 "register_operand")))) + (match_operand:VWEXTI 3 "register_operand")))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + insn_code icode = code_for_pred_widen_mul_plus_u_vx (<MODE>mode); + rtx v_undef = RVV_VUNDEF(<MODE>mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], v_undef}; + + riscv_vector::emit_vlmax_insn (icode, riscv_vector::TERNARY_OP, ops); + + DONE; + } + [(set_attr "type" "viwmuladd")]) + ;; ============================================================================= ;; Combine vec_duplicate + op.vv to op.vf ;; Include diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 9d34725a7570..5507feba30ad 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -9044,6 +9044,56 @@ riscv_vector::prepare_ternary_operands (operands); }) +(define_insn "*pred_widen_mul_plus_u_vx<mode>_undef" + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") + (if_then_else:VWEXTI + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") + (match_operand 6 "vector_length_operand" " rvl") + (match_operand 7 "const_int_operand" " i") + (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VWEXTI + (mult:VWEXTI + (zero_extend:VWEXTI + (vec_duplicate:<V_DOUBLE_TRUNC> + (match_operand:<VSUBEL> 3 "register_operand" " rJ"))) + (zero_extend:VWEXTI + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) + (match_operand:VWEXTI 5 "register_operand" " 0")) + (match_operand:VWEXTI 2 "vector_undef_operand")))] + "TARGET_VECTOR" + "vwmaccu.vx\t%0,%z3,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "<MODE>")]) + +(define_expand "@pred_widen_mul_plus_u_vx<mode>" + [(set (match_operand:VWEXTI 0 "register_operand") + (if_then_else:VWEXTI + (unspec:<VM> + [(match_operand:<VM> 1 "vector_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VWEXTI + (mult:VWEXTI + (zero_extend:VWEXTI + (vec_duplicate:<V_DOUBLE_TRUNC> + (match_operand:<VSUBEL> 2 "register_operand"))) + (zero_extend:VWEXTI + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))) + (match_operand:VWEXTI 4 "register_operand")) + (match_operand:VWEXTI 5 "vector_merge_operand")))] + "TARGET_VECTOR" + { + riscv_vector::prepare_ternary_operands (operands); + }) + (include "autovec.md") (include "autovec-opt.md") (include "sifive-vector.md")
