The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
49a556bfe79b... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB
It previously pointed to:
d7ba1779cbb6... [PR rtl-optimization/122321][RISC-V] Bounds check another a
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
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d7ba177... [PR rtl-optimization/122321][RISC-V] Bounds check another a
97ea68a... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR
cf6524b... [RISC-V] Reorder ready queue slightly to avoid unnecessary
8b85633... niter: Use ranger to query ctz range.
ce5a7af... [PATCH v2] RISC-V: avlprop: Scale AVL by subreg ratio [PR12
931ca9c... RISC-V: Clean up build warnings for VLS calling convention
6fa1f3e... Skip riscv/rvv/xtheadvector/pr116593.C if not hostedlib
f05c6a3... RISC-V: Add testsuite for fixed-length vector calling conve
e5197bd... RISC-V: Add testsuite for fixed-length vector calling conve
ca0ec18... RISC-V: Implement standard fixed-length vector calling conv
da46e89... [RISC-V][PR target/64345][PR tree-optimization/80770] Impro
f40ba16... Increase NUM_ABI_IDS to support RISC-V VLS calling conventi
32f364f... riscv: Fix gimple folding of the vset* intrinsics [PR122270
820e0ef... [PATCH v2] RISC-V: Fix moving data from V_REGS to GR_REGS b
9e9290c... Fix minor RISC-V testsuite failure
f4b98ca... Fix minor testsuite scan failures for RISC-V
3972243... RISC-V: Add testcase for unsigned scalar SAT_MUL form 6
656bde9... RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine
a755d52... [PATCH v3] RISC-V: Implement RISC-V profile macro support
b5439d3... [RISC-V][PR target/120811] Improving address reloads in LRA
454f0a3... [PR target/119587] RISC-V: xtheadmemidx: Split slli.uw patt
5969f6b... [RISC-V] Improve subword atomic patterns in sync.md
a3d5eee... RISC-V: Add test for vec_duplicate + vwsubu.wv combine with
303c703... RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on G
0053ee4... RISC-V: Allow VLS types using up to LMUL 8
660dfc3... [PATCH] RISC-V: Fix slide pattern recognition [PR122124]
cd6efdb... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
0201049... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
6b3e1ae... Fixup merge conflict
3bf5567... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
036f356... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
080fb4d... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
b3a9023... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
7a1b48f... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
15ea306... [RISC-V][PR target/122106] Add missing predicate on crc exp
1c0e36b... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
ff5fe6a... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
2136b5d... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
12ef1c3... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
e2f1a28... RISC-V: Improve slide patterns recognition
c04f130... RISC-V: Only Save/Restore required registers for ILP32E/LP6
a339781... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
3ff97d3... RISC-V: Correct lmul estimation
6dfaa88... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
ccaaf71... [PR tree-optimization/58727] Don't over-simplify constants`
3306783... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
5f82563... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
f50e6a9... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
6038958... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
1155cb2... RISC-V: Allow profiles input in '--with-arch' option.
fd28c51... RISC-V: Configure Profiles definitions in the definition fi
f4bc298... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
41f72dd... Widening-Mul: Refine build_and_insert_cast when rhs is cast
1efc182... RISC-V: Fix vendor intrinsic tests for disabled multilib co
68d01ef... RISC-V: Support vnclip idiom testcase [PR120378]
ca10dea... Match: Support SAT_TRUNC variant NARROW_CLIP
b65c2f9... [RISC-V] Adjust ABI specification in recently added Andes t
6c92582... RISC-V: Suppress cross CC sibcall optimization from vector
250a183... RISC-V: Add min/max patterns for ifcvt.
5b68975... ifcvt: Clarify if_info.original_cost.
9a467a7... RISC-V: Fix can_find_related_mode_p for VLS types
3ec5483... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
86cc6a8... RISC-V: Add pattern for vector-scalar single widening float
7cb1fbc... RISC-V: Add pattern for vector-scalar dual widening floatin
292404d... RISC-V: Add pattern for vector-scalar single widening float
f85fe1f... RISC-V: Add pattern for vector-scalar widening floating-poi
91d9bd0... RISC-V: Adjust tt-ascalon-d8 branch cost
1ac4f1a... RISC-V: Add pattern for vector-scalar single-width floating
02e2f57... RISC-V: Add pattern for vector-scalar single-width floating
7e7b99a... RISC-V: Add pattern for vector-scalar single-width floating
cc55806... RISC-V: Add pattern for vector-scalar widening floating-poi
161dd9b... RISC-V: Add patterns for vector-scalar IEEE floating-point
e920c4c... gcc: introduce the dep_fusion pass
3da43d9... RISC-V: Add support for the XAndesvdot ISA extension.
5c723df... [RISC-V] Fix ordering of pipeline models
2479462... RISC-V: Add support for the XAndesvpackfph ISA extension.
a0ac3ac... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
ac28efe... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
0b10063... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
70d5fe8... dep_fusion: Fix if target does not have macro fusion [PR121
99827c2... gcc: introduce the dep_fusion pass
17ea4ff... RISC-V: Add support for the XAndesvsintload ISA extension.
14bf41e... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
e1bd1ba... RISC-V: Add tt-ascalon-d8 pipeline description
0964598... [RISC-V] Adjust recently added test
d3e072d... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
e78ed90... RISC-V: Allow errors to be suppressed when parsing architec
0acd8e5... RISC-V: Adjust the vmacc.vx combine test cases
9994c71... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
3509c9a... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
87199b0... RISC-V: Fix extension subset check in riscv_can_inline_p
15fe0d9... RISC-V: Add support for the XAndesbfhcvt ISA extension.
9ce705d... RISC-V: Add support for the XAndesperf ISA extension.
5def5b4... RISC-V: Add basic XAndes vendor extension support.
822db7e... RISC-V: Add pattern for vector-scalar floating-point max
91f730b... [RISC-V][PR target/121213] Avoid unnecessary sign extension
9116962... RISC-V: Fix is_vlmax_len_p and use for strided ops.
cea2296... RISC-V: Add Zbb extension sext testcase.
55e2baa... RISC-V: Update Zba 'shNadd.uw' testcase.`
30f79cd... RISC-V: Remove unused print_ext_doc_entry function [NFC]
b4a4a4c... [RISC-V] Improve initial RTL generation for SImode adds on
8d40f65... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
8ac90c7... RISC-V: Add patterns for vector-scalar IEEE floating-point
2758230... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
96b4878... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
f32be7a... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
3c7d91d... RISC-V: Add pattern for vector-scalar floating-point min
2945f75... Remove xfail marker on RISC-V test
41d5505... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
31dd9b9... More RISC-V testsuite hygiene
55c0639... [committed] RISC-V Testsuite hygiene
4bcec61... [PATCH] RISC-V: Add pattern for reverse floating-point divi
b35987c... [PATCH] RISC-V: Add pattern for vector-scalar single-width
44627d0... Fix RISC-V bootstrap
3f12525... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
0a60a40... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
70dd601... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
87ce970... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
d8368df... Fix invalid right shift count with recent ifcvt changes
dd14b91... [PR rtl-optimization/120553] Improve selecting between cons
9cf545f... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
1ebaea7... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
72750aa... [PR target/121213] Avoid unnecessary constant load in amosw
fd391fa... regrename: treat writes as reads for fused instruction pair
7c4a8c7... ira: tie output allocnos for fused instruction pairs
e48735b... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
734eca2... RISC-V: Update the comments of vx combine [NFC]
8e38b8d... RISC-V: Add missed DONE for vx combine pattern [NFC]
8f57a53... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
4cb6706... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
f6809e0... [RISC-V][PR target/121531] Cover missing insn types in p400
cef6d72... [RISC-V][PR target/121160] Avoid bogus force_reg call
20918a8... [RISC-V][PR target/121113] Handle HFmode in various insn re
00ef6ba... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
6872856... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
53ee95f... RISC-V: Expand const_vector with 2 elts per pattern.
db28ef6... Improve initial code generation for addsi/adddi
d0230a0... Don't run tests requiring "B" on designs without "B"
8257271... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
f3e904c... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
c8a70b2... RISC-V: Read extension data from riscv-ext*.def for arch-ca
07b8e32... RISC-V: Support -march=unset
e8f3ac0... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
f546227... RISC-V: Add testcases for signed avg ceil vx combine
8ef5e8a... RISC-V: Adding H to the canonical order [PR121312]
164a85d... RISC-V: Add testcases for unsigned avg ceil vx combine.
fdc566a... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
1a1a765... RISC-V: Remove use of structured binding to fix compiler wa
7d0c658... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
9f52e74... RISC-V: Add test case for vaadd.vx combine polluting VXRM
7671400... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
9575fc1... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
5c4ef2d... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
7636483... RISC-V: Fix another vf FP16 combine run test failures
9e24c11... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
963a83d... RISC-V: Prepare dynamic LMUL heuristic for SLP.
bd4cd86... RISC-V: Remove user-level interrupts
2d24fbe... RISC-V: Add support for resumable non-maskable interrupt (R
5b1be4b... riscv: testsuite: Fix misalignment check.
077b218... RISC-V: Add test case for vx combine polluting VXRM
cf194bc... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
6c0993c... RISC-V: Rework broadcast handling [PR121073].
cb813e3... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
3da86ad... Change bellow in comments to below
0758b4e... [RISC-V] Restrict generic-vector-ooo DFA
9fbe96e... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
d2ee98c... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
4263f17... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
9474861... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
f3b6b6f... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
c798ab3... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
bb91212... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
d48bd8f... RISC-V: Refine the test case for vector avg_floor and avg_c
a8f81e8... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
9c85a3c... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
9dfc310... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
a3c1aea... RISC-V: Support RVVDImode for avg3_ceil auto vect
d703817... RISC-V: Fix vsetvl merge rule.
c27d0b1... RISC-V: Refine the scalar SAT_* test cases
223b5e2... RISC-V: Support RVVDImode for avg3_floor auto vect
4661020... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
13c65e0... RISC-V: Add testcase for rv32 SAT_MUL from uint64
a750800... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
f4fdee4... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
51a049f... RISC-V: Make zero-stride load broadcast a tunable.
8655a4b... [RISC-V] Detect new fusions for RISC-V
9823a6a... RISCV: Remove the v extension requirement for sat scalar ru
ba456f4... RISC-V: Add test for vec_duplicate + vssub.vv combine case
13bfa93... RISC-V: Add test for vec_duplicate + vssub.vv combine case
50e3ef0... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
4959c80... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
0692fe7... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
1d2c4b9... [RISC-V][PR target/120642] Avoid propagating constant AVL f
eaa4d0b... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
603c77e... RISC-V: Do not use vsetivli for THeadVector.
5e6275f... RISC-V: Ignore non-types in builtin function hash.
5e99664... [committed][RISC-V] Fix testsuite fallout from check-functi
4faca02... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
71852aa... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
512dada... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
784e08c... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
f85bccd... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
34d0d36... [RISC-V] Add basic instrumentation to fusion detection
4af7efa... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
aaba6bd... Refactor record_function_versions.
3a8762c... [RISC-V][PR target/118886] Refine when two insns are signal
29e0bf3... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
1eb6c4f... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
d3bb888... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
892fcd2... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
ef6dbb3... RISC-V: Reconcile the existing test due to cost model chang
7c6e572... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
5b557e4... RISC-V: Ignore -Oz for most rvv testcase [NFC]
35c93d8... RISC-V: Primary vector pipeline model for sifive 7 series
953e550... RISC-V: Adding B ext, fp16 and missing scalar instruction t
2c52c26... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
d3fc411... RISC-V: Refactor the function bitmap_union_of_preds_with_en
556e7e2... RISC-V: Add pipeline-checker script
2d9da64... [RISC-V][PR target/119971] Avoid losing shift count masking
04cb23c... RISC-V: update prepare_ternary_operands to handle vector-sc
113fda1... RISC-V: Fix build issue
d485714... RISC-V: Add comment and reorder the the include files in ri
13796fc... RISC-V: Add Profiles RVA/B23S64 support.
0aece63... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
ab2166d... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
8c2c52d... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
1fe100e... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
d9f945f... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
2aacb8f... RISC-V: Fix ICE for expand_select_vldi [PR120652]
d6bc248... [RISC-V] Force several tests to use rocket tuning
254a6cd... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
b49ba3c... RISC-V: Add test for vec_duplicate + vminu.vv combine case
faa5a0d... RISC-V: Add test for vec_duplicate + vminu.vv combine case
c8087fe... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
41343fa... RISC-V: Add generic tune as default.
db00246... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
34fc216... RISC-V: Adding cost model for zilsd
78ae220... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
2026be0... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
78c02e3... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
75e30c9... [PATCH v1] RISC-V: Use scratch reg for loop control
b2c5e5d... RISC-V: Add -fno-pie flags to testcases
ee71dcf... RISC-V: Refine VX combine test case 0 to avoid code duplica
d72c0f9... RISC-V: Update Profiles string in RV23.
1702d4b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
88dc996... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
eb245c6... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
42dd07d... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
1112f23... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
7725094... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
2807d58... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
7ded99c... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
55d6bf2... RISC-V: Prevent speculative vsetvl insn scheduling
87a91f7... RISC-V: Add patterns for vector-scalar negate-(multiply-add
b257752... RISC-V: testsuite: fix an obvious build error
d7c0cae... RISC-V: Regen riscv-ext.texi [NFC]
a6fa625... RISC-V: Add test for vec_duplicate + vremu.vv combine case
0f36ec2... RISC-V: Add test for vec_duplicate + vremu.vv combine case
dd66b8e... RISC-V: Reconcile the existing test for vremu.vx combine
68892a7... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
106a5b6... [RISC-V] Enable more if-conversion on RISC-V
dfdba84... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
119fcab... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
a863116... RISC-V: Reconcile the existing test for vrem.vx combine
91d7d08... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
b7c0370... RISC-V: frm/mode-switch: robustify call_insn backtracking [
eaad234... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
e792a4d... RISC-V: frm/mode-switch: remove dubious frm edge insertion
a412b30... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
81d6dfe... [RISC-V] Handle 32bit operands in condition for conditional
f33f7c5... [to-be-committed][RISC-V] Handle 32bit operands in conditio
d96055f... RISC-V: Reconcile the existing test for vdivu.vx combine
327bbd4... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
5aeb35f... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
f650868... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
170b05d... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
3b4faa2... [RISC-V] Improve signed division by 2^n
d8b5824... RISC-V: Don't use structured binding in riscv-common.cc
4d08c11... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
35b6592... [RISC-V] Improve sequences to generate -1, 1 in some cases.
00797b0... RISC-V: Support Ssu64xl extension.
8b3aef1... RISC-V: Support Sstvecd extension.
6f82f85... RISC-V: Support Sstvala extension.
ba09a6b... RISC-V: Support Sscounterenw extension.
7fbd8c3... RISC-V: Support Ssccptr extension.
c4bfa6c... RISC-V: Support Smrnmi extension.
3ba2215... RISC-V: Support Sm/scsrind extensions.
85353d4... RISC-V: Update extension defination.
210d65a... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
e7fd3f3... [PATCH v2] RISC-V: Add svbare extension.
d004182... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
df3172f... RISC-V: Add Shlcofideleg extension.
7c4f86d... RISC-V: Reconcile the existing test for vdiv.vx combine
6cc972e... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
c38c393... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
14700cc... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
cb84104... RISC-V: Use helper function to get FPR to VR move cost
c9ae6a2... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
1eca67a... [PATCH] RISC-V: Add smcntrpmf extension.
31d47cf... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
66851c7... RISC-V: Implement full-featured iterator for riscv_subset_l
b9e9f98... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
617b47a... RISC-V: Fix line too long format issue for autovect.md [NFC
ed59a0b... RISC-V: Add test cases for avg_ceil vaadd implementation
f9199f3... RISC-V: Reconcile the existing test for avg_ceil
b45f075... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
c9851de... RISC-V: Add minimal support of double trap extension 1.0
8910052... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
d351ef7... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
8385aa3... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
154bd42... RISC-V: Avoid division by zero in check_builtin_call [PR120
dcfd64a... RISC-V: Add test cases for avg_floor vaadd implementation
7395d85... RISC-V: Reconcile the existing test for avg_floor
fd558b7... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
c8369a9... [RISC-V] Add andi+bclr synthesis
74d782a... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
4f8f22a... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
7899526... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
9b11324... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
5a79df6... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
de9c3a5... [RISC-V] shift+and+shift for logical and synthesis
3c66d5d... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
d37d366... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
798b899... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
77192f9... RISC-V: Support CPUs in -march.
df37c18... RISC-V: Add autovec mode param.
539ffb6... RISC-V: Default-initialize variable.
2311953... RISC-V: Fix some dynamic LMUL costing.
7532fea... [RISC-V] Clear both upper and lower bits using 3 shifts
1609201... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
9c26815... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
7f71ec3... [RISC-V] Clear high or low bits using shift pairs
14032ff... [RISC-V] Improve (x << C1) + C2 split code
c0e3e4d... [RISC-V][PR target/120368] Fix 32bit shift on rv64
4bbd7d4... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
f5f7e0f... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
d581894... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
2d65845... [RISC-V] Infrastructure of synthesizing logical AND with co
7337427... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
9f41454... [PATCH v2 1/2] The following changes enable P8700 processor
b71e434... [RISC-V] Avoid multiple assignments to output object
4aea2cc... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
4d7e1e8... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
db456ad... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
ce93cab... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
03e5e07... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
c5e4877... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
970f8be... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
bc2358c... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
059a65a... [committed][RISC-V][PR target/120333] Remove bogus bext pat
621e567... [RISC-V] Fix false positive from Wuninitialized
4934434... RISC-V: Fix the warning of temporary object dangling refere
595a41d... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
1d61114... RISC-V: Support Zilsd code gen
d098416... RISC-V: Add new operand constraint: cR
a8aec95... [RISC-V] Fix ICE due to bogus use of gen_rtvec
47d786d... [RISC-V] Avoid setting output object more than once in IOR/
625c64e... RISC-V: Since the loop increment i++ is unreachable, the lo
f8d49ba... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
59353f7... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
c8f3582... Make end_sequence return the insn sequence
2ee0372... RISC-V: Reuse test name for vx combine test data [NFC]
9f7bbb6... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
f06c232... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
6aab85f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
cf19efc... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
08d0138... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
777f3f5... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
ca9a2cc... RISC-V: Adjust vx combine test case to avoid name conflict
788b0b3... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
959ef69... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
c9ec3ca... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
58832b4... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
98c76d6... RISC-V: Add augmented hypervisor series extensions.
96f8d08... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
02feb0a... RISC-V: Regen riscv-ext.opt.urls
cbca3d6... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
b5e5673... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
f520e1a... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
03a0b46... RISC-V: Introduce riscv_ext_info_t to hold extension metada
80abf2b... RISC-V: Adjust riscv_can_inline_p
7b8c03d... RISC-V: Generate extension table in documentation from risc
c80f7cc... RISC-V: Use riscv-ext.def to generate target options and va
67fe251... RISC-V: Introduce riscv-ext*.def to define extensions
1c82aad... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
5f6f46d... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
5698c69... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
dc21dae... RISC-V: Support for zilsd and zclsd extensions.
b6f9046... testsuite: Fix RISC-V arch-52.c format issue.
0199242... RISC-V: Support RISC-V Profiles 23.
512416e... RISC-V: Support RISC-V Profiles 20/22.
1b49bf1... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
d72a139... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
7969760... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
e56b0cc... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
e1ad6ec... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
fa7c218... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
57ffa78... RISC-V: Separate the test running of rvv vx_vf
42b244d... [RISC-V][PR target/120137][PR target/120154] Don't create o
f341dc9... [PATCH] RISC-V: Minimal support for zama16b extension.
ac8523d... [RISC-V] Avoid unnecessary andi with -1 argument
40b0f99... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
f7ff1dd... [PATCH] RISC-V: Recognized svadu and svade extension
50daa71... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
b124e93... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
9187016... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
de6572d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
fe9f4cf... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
3d5f2b4... RISC-V: Add gr2vr cost helper function
7b5b49f... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
1a45d5c... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
ee192c1... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
f08eafd... [V2][RISC-V] Trivial permutation constant derivation
c9c5f13... [RISC-V] Adjust rvv tests after recent jump threading chang
9e77f9c... [PATCH] RISC-V: Implment H modifier for printing the next r
578cf93... [to-be-committed][RISC-V] Adjust testcases and finish regis
18c5238... RISC-V: Remove unnecessary frm restore volatile define_insn
e229173... RISC-V: Allow different dynamic floating point mode to be m
9fcbe24... RISC-V: Fix missing implied Zicsr from Zve32x
3e08742... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
889bd8c... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
8c4be6a... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
16d46b7... RISC-V: Extract vector stepped for expand_const_vector [NFC
e066eff... RISC-V: Extract vector duplicate for expand_const_vector [N
ccdcf87... RISC-V: Extract vec_series for expand_const_vector [NFC]
3b73e0c... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
d772530... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
7f8f524... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
d8e409a... [riscv] vec_dup immediate constants in pred_broadcast expan
47518d2... [RISC-V][PR target/119865] Don't free ggc allocated memory
7022dee... [RISC-V][PR target/118410] Improve code generation for some
559c051... [RISC-V] Fix missed bext discovery
933bc9d... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
4b1d120... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
a759907... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
49a556b... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB
ef0c01c... RISC-V: Add test for vec_duplicate + vwmaccu.vv combine wit
2f77eea... RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmac
78247a3... [RISC-V] Ignore useless zero-initialization in conditional
e25d12b... [RISC-V][PR 121136] Improve various tests which only need t
b9cc894... RISC-V: testsuite: Fix pr119115.c.
8a41790... [PR rtl-optimization/122536] Fix guard against variable bit
7c1c6dc... RISC-V: Fix the ABI of empty unions and zero length array i
0f696a5... [RISC-V][PR tree-optimization/52345] Optimize testing multi
69c14c3... [RISC-V] Expose sign extension for 32 bit rotates by consta
c47fb95... gcc: Drop junk vim backup file
f34fabb... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR
d650cfd... [RISC-V] Reorder ready queue slightly to avoid unnecessary
c4ab45c... niter: Use ranger to query ctz range.
b58620d... [PATCH v2] RISC-V: avlprop: Scale AVL by subreg ratio [PR12
764cc65... RISC-V: Clean up build warnings for VLS calling convention
b12adbc... Skip riscv/rvv/xtheadvector/pr116593.C if not hostedlib
0c4eb2e... RISC-V: Add testsuite for fixed-length vector calling conve
c9cf3b1... RISC-V: Add testsuite for fixed-length vector calling conve
cea619a... RISC-V: Implement standard fixed-length vector calling conv
d933f1a... [RISC-V][PR target/64345][PR tree-optimization/80770] Impro
5c37281... Increase NUM_ABI_IDS to support RISC-V VLS calling conventi
524de2c... [PATCH v2] RISC-V: Fix moving data from V_REGS to GR_REGS b
8592daf... Fix minor RISC-V testsuite failure
2025d31... Fix minor testsuite scan failures for RISC-V
e79b74f... RISC-V: Add testcase for unsigned scalar SAT_MUL form 6
97b5c1d... RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine
e059d4b... [PATCH v3] RISC-V: Implement RISC-V profile macro support
48acd75... [RISC-V][PR target/120811] Improving address reloads in LRA
87cf04d... [PR target/119587] RISC-V: xtheadmemidx: Split slli.uw patt
bf59675... [RISC-V] Improve subword atomic patterns in sync.md
f7b7714... RISC-V: Add test for vec_duplicate + vwsubu.wv combine with
5208086... RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on G
5a758e9... RISC-V: Allow VLS types using up to LMUL 8
ffd88ce... [PATCH] RISC-V: Fix slide pattern recognition [PR122124]
2c17dc4... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
cd279de... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
2820c2f... Fixup merge conflict
b29241a... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
37e5606... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
eb239c5... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
6b730ee... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
9b79a0e... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
eca3615... [RISC-V][PR target/122106] Add missing predicate on crc exp
1f3af2a... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
3e45271... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
a0ea965... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
c2b587f... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
8a1e591... RISC-V: Improve slide patterns recognition
9e71740... RISC-V: Only Save/Restore required registers for ILP32E/LP6
399946d... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
ef71f3f... RISC-V: Correct lmul estimation
1ad8b60... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
c8681e0... [PR tree-optimization/58727] Don't over-simplify constants`
14b011a... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
16405b3... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
6110a72... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
28604e9... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
c35b44c... RISC-V: Allow profiles input in '--with-arch' option.
b0d7b51... RISC-V: Configure Profiles definitions in the definition fi
53a8649... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
82646da... Widening-Mul: Refine build_and_insert_cast when rhs is cast
19ac053... RISC-V: Fix vendor intrinsic tests for disabled multilib co
52c3602... RISC-V: Support vnclip idiom testcase [PR120378]
4add0df... Match: Support SAT_TRUNC variant NARROW_CLIP
61b4776... [RISC-V] Adjust ABI specification in recently added Andes t
738d515... RISC-V: Suppress cross CC sibcall optimization from vector
c2baf8d... RISC-V: Add min/max patterns for ifcvt.
503fcdc... ifcvt: Clarify if_info.original_cost.
e071943... RISC-V: Fix can_find_related_mode_p for VLS types
d3adcee... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
951b71c... RISC-V: Add pattern for vector-scalar single widening float
d34b34d... RISC-V: Add pattern for vector-scalar dual widening floatin
4b9d183... RISC-V: Add pattern for vector-scalar single widening float
0674ceb... RISC-V: Add pattern for vector-scalar widening floating-poi
0202e91... RISC-V: Adjust tt-ascalon-d8 branch cost
0ce7c88... RISC-V: Add pattern for vector-scalar single-width floating
51614ae... RISC-V: Add pattern for vector-scalar single-width floating
e385344... RISC-V: Add pattern for vector-scalar single-width floating
7ad7d8c... RISC-V: Add pattern for vector-scalar widening floating-poi
c90bdc6... RISC-V: Add patterns for vector-scalar IEEE floating-point
023ccbf... gcc: introduce the dep_fusion pass
c3c15eb... RISC-V: Add support for the XAndesvdot ISA extension.
1af85ce... [RISC-V] Fix ordering of pipeline models
523b318... RISC-V: Add support for the XAndesvpackfph ISA extension.
15174fb... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
fd92765... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
0fac516... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
7611357... dep_fusion: Fix if target does not have macro fusion [PR121
4237e95... gcc: introduce the dep_fusion pass
1b157cd... RISC-V: Add support for the XAndesvsintload ISA extension.
06561ca... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
1b5374b... RISC-V: Add tt-ascalon-d8 pipeline description
186039c... [RISC-V] Adjust recently added test
55565fd... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
9eb00cd... RISC-V: Allow errors to be suppressed when parsing architec
c9b62a5... RISC-V: Adjust the vmacc.vx combine test cases
7c76a52... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
a70aa7f... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
08e5b06... RISC-V: Fix extension subset check in riscv_can_inline_p
099b2e5... RISC-V: Add support for the XAndesbfhcvt ISA extension.
edab9d2... RISC-V: Add support for the XAndesperf ISA extension.
237471b... RISC-V: Add basic XAndes vendor extension support.
d69fa45... RISC-V: Add pattern for vector-scalar floating-point max
3f5b181... [RISC-V][PR target/121213] Avoid unnecessary sign extension
a527df8... RISC-V: Fix is_vlmax_len_p and use for strided ops.
e12dd4c... RISC-V: Add Zbb extension sext testcase.
eca0c44... RISC-V: Update Zba 'shNadd.uw' testcase.`
7d2ccb7... RISC-V: Remove unused print_ext_doc_entry function [NFC]
b848885... [RISC-V] Improve initial RTL generation for SImode adds on
1077d36... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
68dc806... RISC-V: Add patterns for vector-scalar IEEE floating-point
cb6a9c9... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
a44f6de... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
1920d49... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
b092154... RISC-V: Add pattern for vector-scalar floating-point min
a5b607a... Remove xfail marker on RISC-V test
16d9ee1... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
09cc9f8... More RISC-V testsuite hygiene
ef9893a... [committed] RISC-V Testsuite hygiene
4df0cb8... [PATCH] RISC-V: Add pattern for reverse floating-point divi
7140bbb... [PATCH] RISC-V: Add pattern for vector-scalar single-width
4f7b34c... Fix RISC-V bootstrap
fbaa711... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
4b9d8dd... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
ed331e7... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
a71bca7... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
f268cd4... Fix invalid right shift count with recent ifcvt changes
2be5287... [PR rtl-optimization/120553] Improve selecting between cons
3a66728... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
f9f705f... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
c35a012... [PR target/121213] Avoid unnecessary constant load in amosw
dd6dfcb... regrename: treat writes as reads for fused instruction pair
7964e52... ira: tie output allocnos for fused instruction pairs
7d1700f... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
d62ba04... RISC-V: Update the comments of vx combine [NFC]
f515dd7... RISC-V: Add missed DONE for vx combine pattern [NFC]
9ed4cb1... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
34b797c... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
5f8f1f5... [RISC-V][PR target/121531] Cover missing insn types in p400
34e2bac... [RISC-V][PR target/121160] Avoid bogus force_reg call
06fdf31... [RISC-V][PR target/121113] Handle HFmode in various insn re
b2851be... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
748b095... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
7a6c62f... RISC-V: Expand const_vector with 2 elts per pattern.
9b861c7... Improve initial code generation for addsi/adddi
b3ebae3... Don't run tests requiring "B" on designs without "B"
72f09a0... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
b93fd96... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
751098f... RISC-V: Read extension data from riscv-ext*.def for arch-ca
bed4514... RISC-V: Support -march=unset
5e8ee2d... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
b6a17bb... RISC-V: Add testcases for signed avg ceil vx combine
a7be247... RISC-V: Adding H to the canonical order [PR121312]
9b47062... RISC-V: Add testcases for unsigned avg ceil vx combine.
0621b49... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
d3f1692... RISC-V: Remove use of structured binding to fix compiler wa
b92595e... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
62be3ba... RISC-V: Add test case for vaadd.vx combine polluting VXRM
db2de38... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
6015839... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
90080eb... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
f7cbdde... RISC-V: Fix another vf FP16 combine run test failures
a12d8cf... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
577312c... RISC-V: Prepare dynamic LMUL heuristic for SLP.
a2cc047... RISC-V: Remove user-level interrupts
55119a0... RISC-V: Add support for resumable non-maskable interrupt (R
13826c1... riscv: testsuite: Fix misalignment check.
6bd7a23... RISC-V: Add test case for vx combine polluting VXRM
ea980ad... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
c032e32... RISC-V: Rework broadcast handling [PR121073].
7b1a826... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
1c8654d... Change bellow in comments to below
8e287b7... [RISC-V] Restrict generic-vector-ooo DFA
452b351... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
1df11ca... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
8ee5487... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
33accd2... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
2cb88af... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
fff4c08... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
64e67cf... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
3d41018... RISC-V: Refine the test case for vector avg_floor and avg_c
3620e65... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
6913dd0... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
f2140dc... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
4ab0159... RISC-V: Support RVVDImode for avg3_ceil auto vect
92b8d38... RISC-V: Fix vsetvl merge rule.
4b8124f... RISC-V: Refine the scalar SAT_* test cases
b8ba5b2... RISC-V: Support RVVDImode for avg3_floor auto vect
75111e5... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
ff8371e... RISC-V: Add testcase for rv32 SAT_MUL from uint64
83d354a... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
4ffac49... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
e51a9ad... RISC-V: Make zero-stride load broadcast a tunable.
97ab536... [RISC-V] Detect new fusions for RISC-V
d0297c1... RISCV: Remove the v extension requirement for sat scalar ru
4abfd77... RISC-V: Add test for vec_duplicate + vssub.vv combine case
0e095e0... RISC-V: Add test for vec_duplicate + vssub.vv combine case
9e1867e... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
488b4ba... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
118aff9... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
6ea699a... [RISC-V][PR target/120642] Avoid propagating constant AVL f
82ebbbe... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
5abbd77... RISC-V: Do not use vsetivli for THeadVector.
14f2195... RISC-V: Ignore non-types in builtin function hash.
b3b3f52... [committed][RISC-V] Fix testsuite fallout from check-functi
c6d0162... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
2497225... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
3b10f41... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
267bb15... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
394163e... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
378252c... [RISC-V] Add basic instrumentation to fusion detection
3ae5ced... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
e6f6302... Refactor record_function_versions.
303cd16... [RISC-V][PR target/118886] Refine when two insns are signal
11de7b0... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
c73aa74... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
a93e5b9... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
41a01b9... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
0f6f150... RISC-V: Reconcile the existing test due to cost model chang
0763090... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
f296fdc... RISC-V: Ignore -Oz for most rvv testcase [NFC]
6a3a4ad... RISC-V: Primary vector pipeline model for sifive 7 series
ef665de... RISC-V: Adding B ext, fp16 and missing scalar instruction t
41b544d... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
12abc86... RISC-V: Refactor the function bitmap_union_of_preds_with_en
701b8e4... RISC-V: Add pipeline-checker script
99044d8... [RISC-V][PR target/119971] Avoid losing shift count masking
403b8dd... RISC-V: update prepare_ternary_operands to handle vector-sc
cd04d09... RISC-V: Fix build issue
3407c78... RISC-V: Add comment and reorder the the include files in ri
e127335... RISC-V: Add Profiles RVA/B23S64 support.
f056ca8... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
68b7028... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
d605de9... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
cd6b075... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
e44e7ef... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
495cb9e... RISC-V: Fix ICE for expand_select_vldi [PR120652]
f786ba1... [RISC-V] Force several tests to use rocket tuning
d858c51... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
d1e26a9... RISC-V: Add test for vec_duplicate + vminu.vv combine case
6f5c281... RISC-V: Add test for vec_duplicate + vminu.vv combine case
74a44e1... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
dd9082d... RISC-V: Add generic tune as default.
baadc0f... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
b6c47d1... RISC-V: Adding cost model for zilsd
ff7641c... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
0eab021... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
d86789f... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
dca4700... [PATCH v1] RISC-V: Use scratch reg for loop control
0a20369... RISC-V: Add -fno-pie flags to testcases
2bf997f... RISC-V: Refine VX combine test case 0 to avoid code duplica
844c547... RISC-V: Update Profiles string in RV23.
e62fe3b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
f185bd8... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
55f52e6... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
0a5fbfa... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
d2b56b6... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
5d00cb9... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
0a88e23... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
c5fb12e... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
b02625d... RISC-V: Prevent speculative vsetvl insn scheduling
c9fb4ae... RISC-V: Add patterns for vector-scalar negate-(multiply-add
c209747... RISC-V: testsuite: fix an obvious build error
090258c... RISC-V: Regen riscv-ext.texi [NFC]
fe6a0b0... RISC-V: Add test for vec_duplicate + vremu.vv combine case
740a05e... RISC-V: Add test for vec_duplicate + vremu.vv combine case
e76cd66... RISC-V: Reconcile the existing test for vremu.vx combine
e2277cd... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
ebee7f5... [RISC-V] Enable more if-conversion on RISC-V
e19a852... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
d1c0898... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
582f792... RISC-V: Reconcile the existing test for vrem.vx combine
f941708... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
c570bab... RISC-V: frm/mode-switch: robustify call_insn backtracking [
240e4c9... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
fe7e66f... RISC-V: frm/mode-switch: remove dubious frm edge insertion
c8a9931... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
10c3eb3... [RISC-V] Handle 32bit operands in condition for conditional
74132b8... [to-be-committed][RISC-V] Handle 32bit operands in conditio
594cdb5... RISC-V: Reconcile the existing test for vdivu.vx combine
efb12e0... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
4632b9b... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
b3393aa... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
b5af21b... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
51d8abf... [RISC-V] Improve signed division by 2^n
680d7b9... RISC-V: Don't use structured binding in riscv-common.cc
3df9ac6... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
edcad72... [RISC-V] Improve sequences to generate -1, 1 in some cases.
8326723... RISC-V: Support Ssu64xl extension.
cc34f59... RISC-V: Support Sstvecd extension.
2456f13... RISC-V: Support Sstvala extension.
0e04dd1... RISC-V: Support Sscounterenw extension.
38e23c1... RISC-V: Support Ssccptr extension.
049ed8e... RISC-V: Support Smrnmi extension.
fc30fcb... RISC-V: Support Sm/scsrind extensions.
6c6d4a9... RISC-V: Update extension defination.
3e2f5fd... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
fdee91b... [PATCH v2] RISC-V: Add svbare extension.
54a46f0... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
83eda48... RISC-V: Add Shlcofideleg extension.
dcb4f96... RISC-V: Reconcile the existing test for vdiv.vx combine
c6b888e... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
26f3a68... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
9421f64... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
286d1bb... RISC-V: Use helper function to get FPR to VR move cost
8c06b3d... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
9a0c151... [PATCH] RISC-V: Add smcntrpmf extension.
6aaf988... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
5e5b0d3... RISC-V: Implement full-featured iterator for riscv_subset_l
52b0728... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
d5088a7... RISC-V: Fix line too long format issue for autovect.md [NFC
9cd7639... RISC-V: Add test cases for avg_ceil vaadd implementation
b55ff59... RISC-V: Reconcile the existing test for avg_ceil
03f5f88... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
fd6e46c... RISC-V: Add minimal support of double trap extension 1.0
0b79926... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
8d59ceb... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
2ed7874... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
128ff99... RISC-V: Avoid division by zero in check_builtin_call [PR120
cdf244c... RISC-V: Add test cases for avg_floor vaadd implementation
ed0db9e... RISC-V: Reconcile the existing test for avg_floor
55be552... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
5fe5905... [RISC-V] Add andi+bclr synthesis
62756d5... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
4d87b9f... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
5271cc9... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
c3402a7... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
367fa41... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
1517e60... [RISC-V] shift+and+shift for logical and synthesis
92aaa9a... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
3282576... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
52489a6... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
9bf3f9e... RISC-V: Support CPUs in -march.
f48bdc3... RISC-V: Add autovec mode param.
dcd9d4f... RISC-V: Default-initialize variable.
be1e8ad... RISC-V: Fix some dynamic LMUL costing.
1bb77e9... [RISC-V] Clear both upper and lower bits using 3 shifts
1031246... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
284e3f6... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
92d02da... [RISC-V] Clear high or low bits using shift pairs
ffedbeb... [RISC-V] Improve (x << C1) + C2 split code
6fa2031... [RISC-V][PR target/120368] Fix 32bit shift on rv64
83d1cd5... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
f2827b0... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
2db33cb... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
1ac10ac... [RISC-V] Infrastructure of synthesizing logical AND with co
7f48ec3... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
9b36af9... [PATCH v2 1/2] The following changes enable P8700 processor
808a9f7... [RISC-V] Avoid multiple assignments to output object
3e09287... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
d575be6... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
2737964... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
fd7f4b2... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0343e16... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
3cd2b66... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
8de7b02... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
288cb4d... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
22c685c... [committed][RISC-V][PR target/120333] Remove bogus bext pat
a73035b... [RISC-V] Fix false positive from Wuninitialized
c90ad16... RISC-V: Fix the warning of temporary object dangling refere
8dff2d8... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
10930f0... RISC-V: Support Zilsd code gen
8c1ecef... RISC-V: Add new operand constraint: cR
7e9043a... [RISC-V] Fix ICE due to bogus use of gen_rtvec
63f3df8... [RISC-V] Avoid setting output object more than once in IOR/
ce6e9b8... RISC-V: Since the loop increment i++ is unreachable, the lo
70bd9f9... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
1e507a8... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
67b5ce2... Make end_sequence return the insn sequence
fa3e7fd... RISC-V: Reuse test name for vx combine test data [NFC]
9bedb72... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
0e93b6b... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
8ca0648... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
b6261f1... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
9965d50... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
ecbcbe8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
1ef20cc... RISC-V: Adjust vx combine test case to avoid name conflict
83ac2e0... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
a01c446... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
f52b0e9... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
e4a67bf... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
dd3aadb... RISC-V: Add augmented hypervisor series extensions.
2a502c7... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
f49ead4... RISC-V: Regen riscv-ext.opt.urls
fad4fb0... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
0c8209e... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
c4abc6e... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
618045f... RISC-V: Introduce riscv_ext_info_t to hold extension metada
20b9fd0... RISC-V: Adjust riscv_can_inline_p
a84a47c... RISC-V: Generate extension table in documentation from risc
7e49352... RISC-V: Use riscv-ext.def to generate target options and va
e23b0b0... RISC-V: Introduce riscv-ext*.def to define extensions
98baaab... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
3a4090a... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
a3b35d2... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
2fb113c... RISC-V: Support for zilsd and zclsd extensions.
27934c8... testsuite: Fix RISC-V arch-52.c format issue.
adebc28... RISC-V: Support RISC-V Profiles 23.
cf38c7b... RISC-V: Support RISC-V Profiles 20/22.
a4fbb21... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
82c64f7... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
73c5e10... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
db572c6... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
b3dbc5b... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
9a6b9e5... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
fe0c14e... RISC-V: Separate the test running of rvv vx_vf
b805b78... [RISC-V][PR target/120137][PR target/120154] Don't create o
48c19e9... [PATCH] RISC-V: Minimal support for zama16b extension.
781f15e... [RISC-V] Avoid unnecessary andi with -1 argument
e4e2826... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
7ad2997... [PATCH] RISC-V: Recognized svadu and svade extension
a1eefce... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
228476c... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
68684f1... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
327672c... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
0c385d2... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
16bb734... RISC-V: Add gr2vr cost helper function
741d899... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
0f7c778... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
4b02370... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
4a43a8e... [V2][RISC-V] Trivial permutation constant derivation
2556e8d... [RISC-V] Adjust rvv tests after recent jump threading chang
ac8e04a... [PATCH] RISC-V: Implment H modifier for printing the next r
272c570... [to-be-committed][RISC-V] Adjust testcases and finish regis
09b2ff3... RISC-V: Remove unnecessary frm restore volatile define_insn
52306b3... RISC-V: Allow different dynamic floating point mode to be m
954bcab... RISC-V: Fix missing implied Zicsr from Zve32x
4079e20... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
8fab1bb... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
34a7686... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
599b233... RISC-V: Extract vector stepped for expand_const_vector [NFC
33a386d... RISC-V: Extract vector duplicate for expand_const_vector [N
4dbd3df... RISC-V: Extract vec_series for expand_const_vector [NFC]
30644b7... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
94904e5... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
f67aa38... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
885f7fa... [riscv] vec_dup immediate constants in pred_broadcast expan
092714b... [RISC-V][PR target/119865] Don't free ggc allocated memory
1d10214... [RISC-V][PR target/118410] Improve code generation for some
b6f9799... [RISC-V] Fix missed bext discovery
45407ba... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
3e97a50... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
e653247... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
2935ce0... Daily bump. (*)
21cafbf... Daily bump. (*)
70be268... AVR: target/122516: Make attribute "retain" work. (*)
e9b9bc4... AVR: AVR-SD: Put a valid opcode prior to gs() table in .sub (*)
18aded4... Daily bump. (*)
cc39aed... Daily bump. (*)
3c42004... Ada: Fix visibility bug related to target name (*)
934b2d4... c++: Don't constrain template visibility using no-linkage v (*)
7503954... Daily bump. (*)
33eebbf... [PR rtl-optimization/122321][RISC-V] Bounds check another a (*)
f70ea62... riscv: Fix gimple folding of the vset* intrinsics [PR122270 (*)
e3f926b... Daily bump. (*)
a56bab1... AVR: target/122527 -- Don't use __load_N to load from __fla (*)
567744a... AVR: PR122505 - Fix bloated mulpsi3 in the wake of hacking (*)
59213fd... c++/modules: Track all static class variables [PR122421] (*)
1429b8a... Daily bump. (*)
31d3f96... Fortran: IS_CONTIGUOUS and pointers to non-contiguous targe (*)
696bfba... Fortran: fix TRANSFER of subarray component references [PR1 (*)
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