https://gcc.gnu.org/g:03a1951a30c4f512f366d9ff7fb62dc01841cb81
commit r16-6113-g03a1951a30c4f512f366d9ff7fb62dc01841cb81 Author: Jerry Zhang Jian <[email protected]> Date: Sun Dec 14 20:09:56 2025 -0700 [PATCH] RISC-V: Rename UPPERCAE_NAME to UPPERCASE_NAME This is a follow-up to d99af4e12bf8. gcc/ChangeLog: * config/riscv/gen-riscv-ext-opt.cc: Rename UPPERCAE_NAME to UPPERCASE_NAME. * config/riscv/gen-riscv-ext-texi.cc: Likewise. * config/riscv/riscv-ext-corev.def: Likewise. * config/riscv/riscv-ext-sifive.def: Likewise. * config/riscv/riscv-ext-thead.def: Likewise. * config/riscv/riscv-ext-ventana.def: Likewise. Diff: --- gcc/config/riscv/gen-riscv-ext-opt.cc | 6 +++--- gcc/config/riscv/gen-riscv-ext-texi.cc | 2 +- gcc/config/riscv/riscv-ext-corev.def | 10 +++++----- gcc/config/riscv/riscv-ext-sifive.def | 10 +++++----- gcc/config/riscv/riscv-ext-thead.def | 26 +++++++++++++------------- gcc/config/riscv/riscv-ext-ventana.def | 2 +- 6 files changed, 28 insertions(+), 28 deletions(-) diff --git a/gcc/config/riscv/gen-riscv-ext-opt.cc b/gcc/config/riscv/gen-riscv-ext-opt.cc index 1ca339c60f0b..9b6fb4022340 100644 --- a/gcc/config/riscv/gen-riscv-ext-opt.cc +++ b/gcc/config/riscv/gen-riscv-ext-opt.cc @@ -37,7 +37,7 @@ main () puts ("; Please *DO NOT* edit manually."); std::set<std::string> all_vars; -#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ +#define DEFINE_RISCV_EXT(NAME, UPPERCASE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ all_vars.insert ("riscv_" #FLAG_GROUP "_subext"); @@ -50,10 +50,10 @@ main () printf ("int %s\n\n", var.c_str ()); } -#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ +#define DEFINE_RISCV_EXT(NAME, UPPERCASE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ - puts ("Mask(" #UPPERCAE_NAME ") Var(riscv_" #FLAG_GROUP "_subext)\n"); + puts ("Mask(" #UPPERCASE_NAME ") Var(riscv_" #FLAG_GROUP "_subext)\n"); #include "riscv-ext.def" #undef DEFINE_RISCV_EXT diff --git a/gcc/config/riscv/gen-riscv-ext-texi.cc b/gcc/config/riscv/gen-riscv-ext-texi.cc index c29a375d56c4..e0169910887b 100644 --- a/gcc/config/riscv/gen-riscv-ext-texi.cc +++ b/gcc/config/riscv/gen-riscv-ext-texi.cc @@ -75,7 +75,7 @@ main () puts ("@samp{zifencei}."); puts (""); -#define DEFINE_RISCV_EXT(NAME, UPPERCAE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ +#define DEFINE_RISCV_EXT(NAME, UPPERCASE_NAME, FULL_NAME, DESC, URL, DEP_EXTS, \ SUPPORTED_VERSIONS, FLAG_GROUP, BITMASK_GROUP_ID, \ BITMASK_BIT_POSITION, EXTRA_EXTENSION_FLAGS) \ print_ext_doc_entry (#NAME, FULL_NAME, DESC, \ diff --git a/gcc/config/riscv/riscv-ext-corev.def b/gcc/config/riscv/riscv-ext-corev.def index eb97399403cd..c60a566eb61b 100644 --- a/gcc/config/riscv/riscv-ext-corev.def +++ b/gcc/config/riscv/riscv-ext-corev.def @@ -23,7 +23,7 @@ Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ DEFINE_RISCV_EXT( /* NAME */ xcvalu, - /* UPPERCAE_NAME */ XCVALU, + /* UPPERCASE_NAME */ XCVALU, /* FULL_NAME */ "Core-V miscellaneous ALU extension", /* DESC */ "", /* URL */ , @@ -36,7 +36,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xcvbi, - /* UPPERCAE_NAME */ XCVBI, + /* UPPERCASE_NAME */ XCVBI, /* FULL_NAME */ "xcvbi extension", /* DESC */ "", /* URL */ , @@ -49,7 +49,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xcvelw, - /* UPPERCAE_NAME */ XCVELW, + /* UPPERCASE_NAME */ XCVELW, /* FULL_NAME */ "Core-V event load word extension", /* DESC */ "", /* URL */ , @@ -62,7 +62,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xcvmac, - /* UPPERCAE_NAME */ XCVMAC, + /* UPPERCASE_NAME */ XCVMAC, /* FULL_NAME */ "Core-V multiply-accumulate extension", /* DESC */ "", /* URL */ , @@ -75,7 +75,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xcvsimd, - /* UPPERCAE_NAME */ XCVSIMD, + /* UPPERCASE_NAME */ XCVSIMD, /* FULL_NAME */ "xcvsimd extension", /* DESC */ "", /* URL */ , diff --git a/gcc/config/riscv/riscv-ext-sifive.def b/gcc/config/riscv/riscv-ext-sifive.def index c8d79da479ca..26d4260914d0 100644 --- a/gcc/config/riscv/riscv-ext-sifive.def +++ b/gcc/config/riscv/riscv-ext-sifive.def @@ -23,7 +23,7 @@ Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ DEFINE_RISCV_EXT( /* NAME */ xsfcease, - /* UPPERCAE_NAME */ XSFCEASE, + /* UPPERCASE_NAME */ XSFCEASE, /* FULL_NAME */ "xsfcease extension", /* DESC */ "", /* URL */ , @@ -36,7 +36,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvcp, - /* UPPERCAE_NAME */ XSFVCP, + /* UPPERCASE_NAME */ XSFVCP, /* FULL_NAME */ "xsfvcp extension", /* DESC */ "", /* URL */ , @@ -49,7 +49,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvfnrclipxfqf, - /* UPPERCAE_NAME */ XSFVFNRCLIPXFQF, + /* UPPERCASE_NAME */ XSFVFNRCLIPXFQF, /* FULL_NAME */ "xsfvfnrclipxfqf extension", /* DESC */ "", /* URL */ , @@ -62,7 +62,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvqmaccdod, - /* UPPERCAE_NAME */ XSFVQMACCDOD, + /* UPPERCASE_NAME */ XSFVQMACCDOD, /* FULL_NAME */ "xsfvqmaccdod extension", /* DESC */ "", /* URL */ , @@ -75,7 +75,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xsfvqmaccqoq, - /* UPPERCAE_NAME */ XSFVQMACCQOQ, + /* UPPERCASE_NAME */ XSFVQMACCQOQ, /* FULL_NAME */ "xsfvqmaccqoq extension", /* DESC */ "", /* URL */ , diff --git a/gcc/config/riscv/riscv-ext-thead.def b/gcc/config/riscv/riscv-ext-thead.def index 327d2ae0d395..c49bd0042035 100644 --- a/gcc/config/riscv/riscv-ext-thead.def +++ b/gcc/config/riscv/riscv-ext-thead.def @@ -23,7 +23,7 @@ Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ DEFINE_RISCV_EXT( /* NAME */ xtheadba, - /* UPPERCAE_NAME */ XTHEADBA, + /* UPPERCASE_NAME */ XTHEADBA, /* FULL_NAME */ "T-head address calculation extension", /* DESC */ "", /* URL */ , @@ -36,7 +36,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadbb, - /* UPPERCAE_NAME */ XTHEADBB, + /* UPPERCASE_NAME */ XTHEADBB, /* FULL_NAME */ "T-head basic bit-manipulation extension", /* DESC */ "", /* URL */ , @@ -49,7 +49,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadbs, - /* UPPERCAE_NAME */ XTHEADBS, + /* UPPERCASE_NAME */ XTHEADBS, /* FULL_NAME */ "T-head single-bit instructions extension", /* DESC */ "", /* URL */ , @@ -62,7 +62,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadcmo, - /* UPPERCAE_NAME */ XTHEADCMO, + /* UPPERCASE_NAME */ XTHEADCMO, /* FULL_NAME */ "T-head cache management operations extension", /* DESC */ "", /* URL */ , @@ -75,7 +75,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadcondmov, - /* UPPERCAE_NAME */ XTHEADCONDMOV, + /* UPPERCASE_NAME */ XTHEADCONDMOV, /* FULL_NAME */ "T-head conditional move extension", /* DESC */ "", /* URL */ , @@ -88,7 +88,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadfmemidx, - /* UPPERCAE_NAME */ XTHEADFMEMIDX, + /* UPPERCASE_NAME */ XTHEADFMEMIDX, /* FULL_NAME */ "T-head indexed memory operations for floating-point registers extension", /* DESC */ "", /* URL */ , @@ -101,7 +101,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadfmv, - /* UPPERCAE_NAME */ XTHEADFMV, + /* UPPERCASE_NAME */ XTHEADFMV, /* FULL_NAME */ "T-head double floating-point high-bit data transmission extension", /* DESC */ "", /* URL */ , @@ -114,7 +114,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadint, - /* UPPERCAE_NAME */ XTHEADINT, + /* UPPERCASE_NAME */ XTHEADINT, /* FULL_NAME */ "T-head acceleration interruption extension", /* DESC */ "", /* URL */ , @@ -127,7 +127,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadmac, - /* UPPERCAE_NAME */ XTHEADMAC, + /* UPPERCASE_NAME */ XTHEADMAC, /* FULL_NAME */ "T-head multiply-accumulate extension", /* DESC */ "", /* URL */ , @@ -140,7 +140,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadmemidx, - /* UPPERCAE_NAME */ XTHEADMEMIDX, + /* UPPERCASE_NAME */ XTHEADMEMIDX, /* FULL_NAME */ "T-head indexed memory operation extension", /* DESC */ "", /* URL */ , @@ -153,7 +153,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadmempair, - /* UPPERCAE_NAME */ XTHEADMEMPAIR, + /* UPPERCASE_NAME */ XTHEADMEMPAIR, /* FULL_NAME */ "T-head two-GPR memory operation extension", /* DESC */ "", /* URL */ , @@ -166,7 +166,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadsync, - /* UPPERCAE_NAME */ XTHEADSYNC, + /* UPPERCASE_NAME */ XTHEADSYNC, /* FULL_NAME */ "T-head multi-core synchronization extension", /* DESC */ "", /* URL */ , @@ -179,7 +179,7 @@ DEFINE_RISCV_EXT( DEFINE_RISCV_EXT( /* NAME */ xtheadvector, - /* UPPERCAE_NAME */ XTHEADVECTOR, + /* UPPERCASE_NAME */ XTHEADVECTOR, /* FULL_NAME */ "xtheadvector extension", /* DESC */ "", /* URL */ , diff --git a/gcc/config/riscv/riscv-ext-ventana.def b/gcc/config/riscv/riscv-ext-ventana.def index deed47f112a5..7ae41b783bce 100644 --- a/gcc/config/riscv/riscv-ext-ventana.def +++ b/gcc/config/riscv/riscv-ext-ventana.def @@ -23,7 +23,7 @@ Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ DEFINE_RISCV_EXT( /* NAME */ xventanacondops, - /* UPPERCAE_NAME */ XVENTANACONDOPS, + /* UPPERCASE_NAME */ XVENTANACONDOPS, /* FULL_NAME */ "Ventana integer conditional operations extension", /* DESC */ "", /* URL */ ,
