https://gcc.gnu.org/g:6b60fa25daeacefd26ae028d47c7f143924a801c
commit 6b60fa25daeacefd26ae028d47c7f143924a801c Author: Michael Meissner <[email protected]> Date: Mon Dec 15 23:08:03 2025 -0500 Revert changes Diff: --- gcc/config.gcc | 18 -- gcc/config/rs6000/float16.cc | 150 -------------- gcc/config/rs6000/float16.md | 282 -------------------------- gcc/config/rs6000/predicates.md | 76 ------- gcc/config/rs6000/rs6000-call.cc | 34 +--- gcc/config/rs6000/rs6000-cpus.def | 13 +- gcc/config/rs6000/rs6000-protos.h | 2 - gcc/testsuite/gcc.target/powerpc/bfloat16-1.c | 34 ---- gcc/testsuite/gcc.target/powerpc/bfloat16-2.c | 72 ------- gcc/testsuite/gcc.target/powerpc/float16-1.c | 34 ---- gcc/testsuite/gcc.target/powerpc/float16-2.c | 73 ------- gcc/testsuite/lib/target-supports.exp | 138 ------------- 12 files changed, 8 insertions(+), 918 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index a1234c4053c4..a9515baa3ee3 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -5847,24 +5847,6 @@ case "${target}" in elif test x$with_long_double_format = xibm; then tm_defines="${tm_defines} TARGET_IEEEQUAD_DEFAULT=0" fi - - # Test if we should enable 16-bit floating point on the platforms - # where we can support __bfloat16 and _Float16. - if test x$with_powerpc_float16 = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DEFAULT=1" - - elif test x$with_powerpc_16bit_floating_point = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DEFAULT=0" - fi - - # Test if we should disable the warning about passing - # and returning 16-bit floating point values. - if test x$with_powerpc_float16_disable_warning = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DISABLE_WARNING=1" - - elif test x$with_powerpc_float16_disable_warning = xno; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DISABLE_WARNING=0" - fi ;; s390*-*-*) diff --git a/gcc/config/rs6000/float16.cc b/gcc/config/rs6000/float16.cc index 2c7b6278a16a..5274a0df962f 100644 --- a/gcc/config/rs6000/float16.cc +++ b/gcc/config/rs6000/float16.cc @@ -183,153 +183,3 @@ fp16_vectorization (enum rtx_code icode, return; } - -/* Expand a bfloat16 scalar floating point operation: - - ICODE: Operation to perform. - RESULT: Result of the operation. - OP1: Input operand1. - OP2: Input operand2. - OP3: Input operand3 or NULL_RTX. - SUBTYPE: Describe the operation. - - The operation is done as a V4SFmode vector operation. This is because - converting BFmode from a scalar BFmode to SFmode to do the operation and - back again takes quite a bit of time. GCC will only generate the native - operation if -Ofast is used. The float16.md code that calls this function - adds various combine operations to do the operation in V4SFmode instead of - SFmode. */ - -void -bfloat16_operation_as_v4sf (enum rtx_code icode, - rtx result, - rtx op1, - rtx op2, - rtx op3, - enum fp16_operation subtype) -{ - gcc_assert (can_create_pseudo_p ()); - - rtx result_v4sf = gen_reg_rtx (V4SFmode); - rtx ops_orig[3] = { op1, op2, op3 }; - rtx ops_v4sf[3]; - size_t n_opts; - - switch (subtype) - { - case FP16_BINARY: - n_opts = 2; - gcc_assert (op3 == NULL_RTX); - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - gcc_assert (icode == FMA); - n_opts = 3; - break; - - default: - gcc_unreachable (); - } - - for (size_t i = 0; i < n_opts; i++) - { - rtx op = ops_orig[i]; - rtx tmp = ops_v4sf[i] = gen_reg_rtx (V4SFmode); - - gcc_assert (op != NULL_RTX); - - /* Remove truncation/extend added. */ - if (GET_CODE (op) == FLOAT_EXTEND || GET_CODE (op) == FLOAT_TRUNCATE) - op = XEXP (op, 0); - - /* Convert operands to V4SFmode format. We use SPLAT for registers to - get the value into the upper 32-bits. We can use XXSPLTW to splat - words instead of VSPLTIH since the XVCVBF16SPN instruction ignores the - odd half-words, and XXSPLTW can operate on all VSX registers instead - of just the Altivec registers. Using SPLAT instead of a shift also - insure that other bits are not a signalling NaN. If we are using - XXSPLTIW or XXSPLTIB to load the constant the other bits are - duplicated. */ - - if (op == CONST0_RTX (SFmode) || op == CONST0_RTX (BFmode)) - emit_move_insn (tmp, CONST0_RTX (V4SFmode)); - - else if (GET_MODE (op) == BFmode) - { - emit_insn (gen_xxspltw_bf (tmp, force_reg (BFmode, op))); - emit_insn (gen_xvcvbf16spn_bf (tmp, tmp)); - } - - else if (GET_MODE (op) == SFmode) - { - if (GET_CODE (op) == CONST_DOUBLE) - { - rtvec v = rtvec_alloc (4); - - for (size_t i = 0; i < 4; i++) - RTVEC_ELT (v, i) = op; - - emit_insn (gen_rtx_SET (tmp, - gen_rtx_CONST_VECTOR (V4SFmode, v))); - } - - else - emit_insn (gen_vsx_splat_v4sf (tmp, - force_reg (SFmode, op))); - } - - else - gcc_unreachable (); - } - - /* Do the operation in V4SFmode. */ - switch (subtype) - { - case FP16_BINARY: - emit_insn (gen_rtx_SET (result_v4sf, - gen_rtx_fmt_ee (icode, V4SFmode, - ops_v4sf[0], - ops_v4sf[1]))); - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - { - rtx op1 = ops_v4sf[0]; - rtx op2 = ops_v4sf[1]; - rtx op3 = ops_v4sf[2]; - - if (subtype == FP16_FMS || subtype == FP16_NFMS) - op3 = gen_rtx_NEG (V4SFmode, op3); - - rtx op_fma = gen_rtx_FMA (V4SFmode, op1, op2, op3); - - if (subtype == FP16_NFMA || subtype == FP16_NFMS) - op_fma = gen_rtx_NEG (V4SFmode, op_fma); - - emit_insn (gen_rtx_SET (result_v4sf, op_fma)); - } - break; - - default: - gcc_unreachable (); - } - - /* Convert V4SF result back to scalar mode. */ - if (GET_MODE (result) == BFmode) - emit_insn (gen_xvcvspbf16_bf (result, result_v4sf)); - - else if (GET_MODE (result) == SFmode) - { - rtx element = GEN_INT (WORDS_BIG_ENDIAN ? 2 : 3); - emit_insn (gen_vsx_extract_v4sf (result, result_v4sf, element)); - } - - else - gcc_unreachable (); -} diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 2d062e762611..2305fe21f137 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -972,285 +972,3 @@ "TARGET_BFLOAT16_HW" "xvcvbf16spn %x0,%x1" [(set_attr "type" "vecperm")]) - -;; Optimize __bfloat16 binary operations. Unlike _Float16 where we -;; have instructions to convert between HFmode and SFmode as scalar -;; values, with BFmode, we only have vector conversions. Thus to do: -;; -;; __bfloat16 a, b, c; -;; a = b + c; -;; -;; the GCC compiler would normally generate: -;; -;; lxsihzx 0,4,2 // load __bfloat16 value b -;; lxsihzx 12,5,2 // load __bfloat16 value c -;; xxsldwi 0,0,0,1 // shift b into bits 16..31 -;; xxsldwi 12,12,12,1 // shift c into bits 16..31 -;; xvcvbf16spn 0,0 // vector convert b into V4SFmode -;; xvcvbf16spn 12,12 // vector convert c into V4SFmode -;; xscvspdpn 0,0 // convert b into SFmode scalar -;; xscvspdpn 12,12 // convert c into SFmode scalar -;; fadds 0,0,12 // add b+c -;; xscvdpspn 0,0 // convert b+c into SFmode memory format -;; xvcvspbf16 0,0 // convert b+c into BFmode memory format -;; stxsihx 0,3,2 // store b+c -;; -;; Using the following combiner patterns, the code generated would now -;; be: -;; -;; lxsihzx 12,4,2 // load __bfloat16 value b -;; lxsihzx 0,5,2 // load __bfloat16 value c -;; xxspltw 12,12,1 // shift b into bits 16..31 -;; xxspltw 0,0,1 // shift c into bits 16..31 -;; xvcvbf16spn 12,12 // vector convert b into V4SFmode -;; xvcvbf16spn 0,0 // vector convert c into V4SFmode -;; xvaddsp 0,0,12 // vector b+c in V4SFmode -;; xvcvspbf16 0,0 // convert b+c into BFmode memory format -;; stxsihx 0,3,2 // store b+c -;; -;; We cannot just define insns like 'addbf3' to keep the operation as -;; BFmode because GCC will not generate these patterns unless the user -;; uses -Ofast. Without -Ofast, it will always convert BFmode into -;; SFmode. - -(define_insn_and_split "*bfloat16_binary_op_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (match_operator:SF 1 "fp16_binary_operator" - [(match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")]))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[2], SFmode) - || bfloat16_bf_operand (operands[3], SFmode))" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (GET_CODE (operands[1]), operands[0], operands[2], - operands[3], NULL_RTX, FP16_BINARY); - DONE; -}) - -(define_insn_and_split "*bfloat16_binary_op_internal2" - [(set (match_operand:BF 0 "vsx_register_operand") - (float_truncate:BF - (match_operator:SF 1 "fp16_binary_operator" - [(match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")])))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[2], SFmode) - || bfloat16_bf_operand (operands[3], SFmode))" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (GET_CODE (operands[1]), operands[0], operands[2], - operands[3], NULL_RTX, FP16_BINARY); - DONE; -}) - -(define_insn_and_split "*bfloat16_fma_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_fma_internal2" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand"))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_fms_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand"))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_fms_internal2" - [(set (match_operand:BF 0 "vsx_register_operand") - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfma_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand"))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfma_internal2" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (float_truncate:BF - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfma_internal3" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (neg:BF - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfms_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfms_internal2" - [(set (match_operand:BF 0 "vsx_register_operand") - (float_truncate:BF - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand"))))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfms_internal3" - [(set (match_operand:BF 0 "vsx_register_operand") - (neg:BF - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand"))))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 6fb14d04c8d2..586b519d375f 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -2249,79 +2249,3 @@ return constant_generates_xxspltiw (&vsx_const); }) - -;; Return 1 if this is a 16-bit floating point operand that can be used -;; in an add, subtract, or multiply operation that uses the vector -;; conversion function. -(define_predicate "fp16_reg_or_constant_operand" - (match_code "reg,subreg,const_double") -{ - if (REG_P (op) || SUBREG_P (op)) - return vsx_register_operand (op, mode); - - if (CONST_DOUBLE_P (op)) - return fp16_xxspltiw_constant (op, mode); - - return false; -}) - -;; Match binary operators where we convert a BFmode operand into a -;; SFmode operand so that we can optimize the BFmode operation to do -;; the operation in vector mode rather than convverting the BFmode to a -;; V8BFmode vector, converting that V8BFmode vector to V4SFmode, and -;; then converting the V4SFmode element to SFmode scalar. -(define_predicate "fp16_binary_operator" - (match_code "plus,minus,mult,smax,smin")) - -;; Match bfloat16/float operands that can be optimized to do the -;; operation in V4SFmode. -(define_predicate "bfloat16_v4sf_operand" - (match_code "reg,subreg,const_double,float_extend,float_truncate") -{ - if (mode != BFmode && mode != SFmode) - return false; - - if (REG_P (op) || SUBREG_P (op)) - return register_operand (op, mode); - - if (CONST_DOUBLE_P (op)) - return true; - - if (GET_CODE (op) == FLOAT_EXTEND) - { - rtx op_arg = XEXP (op, 0); - return (mode == SFmode - && GET_MODE (op_arg) == BFmode - && (REG_P (op_arg) || SUBREG_P (op_arg))); - } - - if (GET_CODE (op) == FLOAT_TRUNCATE) - { - rtx op_arg = XEXP (op, 0); - return (mode == BFmode - && GET_MODE (op_arg) == SFmode - && (REG_P (op_arg) || SUBREG_P (op_arg))); - } - - return false; -}) - -;; Match an operand that originally was an BFmode value to prevent -;; operations involing only SFmode values from being converted to -;; BFmode. -(define_predicate "bfloat16_bf_operand" - (match_code "reg,subreg,const_double,float_extend") -{ - if (mode == BFmode || GET_MODE (op) == BFmode) - return true; - - if (mode != SFmode) - return false; - - if (GET_MODE (op) == SFmode - && GET_CODE (op) == FLOAT_EXTEND - && GET_MODE (XEXP (op, 0)) == BFmode) - return true; - - return false; -}) diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc index 4d55ea2d1b36..41c0d4f71590 100644 --- a/gcc/config/rs6000/rs6000-call.cc +++ b/gcc/config/rs6000/rs6000-call.cc @@ -685,27 +685,17 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, " to enable them", "-maltivec"); } -#if !POWERPC_FLOAT16_DISABLE_WARNING /* Warn that __bfloat16 and _Float16 might be returned differently in the future. The issue is currently 16-bit floating point is returned in floating point register #1 in 16-bit format. We may or may not want to return it as a scalar 64-bit value. */ if (fntype && warn_psabi && !cum->libcall) { - static bool warned_about_float16_return = false; - - if (!warned_about_float16_return) - { - machine_mode ret_mode = TYPE_MODE (TREE_TYPE (fntype)); - - warned_about_float16_return = true; - if (ret_mode == BFmode || ret_mode == HFmode) - warning (OPT_Wpsabi, - "%s might be returned differently in the future", - ret_mode == BFmode ? "__bfloat16" : "_Float16"); - } + machine_mode ret_mode = TYPE_MODE (TREE_TYPE (fntype)); + if (ret_mode == BFmode || ret_mode == HFmode) + warning (OPT_Wpsabi, "%s might be returned differently in the future", + ret_mode == BFmode ? "__bfloat16" : "_Float16"); } -#endif } @@ -1663,23 +1653,13 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) return NULL_RTX; } -#if !POWERPC_FLOAT16_DISABLE_WARNING /* Warn that _Float16 and __bfloat16 might be passed differently in the future. The issue is currently 16-bit floating point values are passed in floating point registers in the native 16-bit format. We may or may not want to pass the value it as a scalar 64-bit value. */ - if (warn_psabi && !cum->libcall && FP16_SCALAR_MODE_P (mode)) - { - static bool warned_about_float16_call = false; - - if (!warned_about_float16_call) - { - warned_about_float16_call = true; - warning (OPT_Wpsabi, "%s might be passed differently in the future", - mode == BFmode ? "__bfloat16" : "_Float16"); - } - } -#endif + if (warn_psabi && !cum->libcall && (mode == BFmode || mode == HFmode)) + warning (OPT_Wpsabi, "%s might be passed differently in the future", + mode == BFmode ? "__bfloat16" : "_Float16"); /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 uses to say fp args were passed in registers. diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index d4b440601eea..d344c1e6925a 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -43,15 +43,6 @@ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) -/* Determine whether to enable 16-bit floating point types on power8 systems - and above. */ -#if POWERPC_FLOAT16_DEFAULT -#define TARGET_16BIT_FLOATING_POINT OPTION_MASK_FLOAT16 - -#else -#define TARGET_16BIT_FLOATING_POINT 0 -#endif - /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ @@ -61,8 +52,7 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_QUAD_MEMORY \ - | OPTION_MASK_QUAD_MEMORY_ATOMIC \ - | TARGET_16BIT_FLOATING_POINT) + | OPTION_MASK_QUAD_MEMORY_ATOMIC) /* ISA masks setting fusion options. */ #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ @@ -139,7 +129,6 @@ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ - | OPTION_MASK_FLOAT16 \ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ | OPTION_MASK_POWER11 \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 3665a405cfd2..dd5fcd69e836 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -271,8 +271,6 @@ enum fp16_operation { extern void fp16_vectorization (enum rtx_code, rtx, rtx, rtx, rtx, enum fp16_operation); -extern void bfloat16_operation_as_v4sf (enum rtx_code, rtx, rtx, rtx, rtx, - enum fp16_operation); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/testsuite/gcc.target/powerpc/bfloat16-1.c b/gcc/testsuite/gcc.target/powerpc/bfloat16-1.c deleted file mode 100644 index bbd6ce1f9373..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/bfloat16-1.c +++ /dev/null @@ -1,34 +0,0 @@ -/* { dg-do run } */ -/* { dg-require-effective-target ppc_bfloat16_runtime } */ -/* { dg-options "-mfloat16 -O2" } */ - -#include <stdlib.h> - -/* This tests whether we can do __bfloat16 calculations either with software - emuluation or via hardware support. */ -volatile __bfloat16 two = 2.0; -volatile __bfloat16 three = 3.0; -volatile __bfloat16 result_add, result_sub, result_mul, result_div; - -int -main (int argc, char *argv[]) -{ - result_add = three + two; - result_sub = three - two; - result_mul = three * two; - result_div = three / two; - - if (((double)result_add) != 5.0) - abort (); - - if (((double)result_sub) != 1.0) - abort (); - - if (((double)result_mul) != 6.0) - abort (); - - if (((double)result_div) != 1.5) - abort (); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/powerpc/bfloat16-2.c b/gcc/testsuite/gcc.target/powerpc/bfloat16-2.c deleted file mode 100644 index 00c70ece1876..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/bfloat16-2.c +++ /dev/null @@ -1,72 +0,0 @@ -/* { dg-do run } */ -/* { dg-require-effective-target ppc_bfloat16_hw } */ -/* { dg-options "-mfloat16 -O2" } */ - -#include <stdlib.h> - -/* On a power10/power11 system, test whether we can do __bfloat16 calculations - with both software emulation (i.e. running the code with -mcpu=power8) and - hardware conversions (i.e. with -mcpu=power10 or -mcpu=power11). - - Power10 supports the XVCVBF16SPN and XVCVSPBF16 instructions that convert between - a vector __bfloat16 and a vector float. */ - -extern void do_power10 (void) __attribute__ ((noinline,target("cpu=power10"))); -extern void do_power8 (void) __attribute__ ((noinline,target("cpu=power8"))); - -volatile __bfloat16 two = 2.0; -volatile __bfloat16 three = 3.0; -volatile __bfloat16 p8_add, p8_sub, p8_mul, p8_div; -volatile __bfloat16 p10_add, p10_sub, p10_mul, p10_div; - -void -do_power8 (void) -{ - p8_add = three + two; - p8_sub = three - two; - p8_mul = three * two; - p8_div = three / two; -} - -void -do_power10 (void) -{ - p10_add = three + two; - p10_sub = three - two; - p10_mul = three * two; - p10_div = three / two; -} - -int -main (int argc, char *argv[]) -{ - do_power8 (); - - if (((double)p8_add) != 5.0) - abort (); - - if (((double)p8_sub) != 1.0) - abort (); - - if (((double)p8_mul) != 6.0) - abort (); - - if (((double)p8_div) != 1.5) - abort (); - - do_power10 (); - - if (((double)p10_add) != 5.0) - abort (); - - if (((double)p10_sub) != 1.0) - abort (); - - if (((double)p10_mul) != 6.0) - abort (); - - if (((double)p10_div) != 1.5) - abort (); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/powerpc/float16-1.c b/gcc/testsuite/gcc.target/powerpc/float16-1.c deleted file mode 100644 index e3a749ebbef8..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/float16-1.c +++ /dev/null @@ -1,34 +0,0 @@ -/* { dg-do run } */ -/* { dg-require-effective-target ppc_float16_runtime } */ -/* { dg-options "-mfloat16 -O2" } */ - -#include <stdlib.h> - -/* This tests whether we can do _Float16 calculations either with software - emuluation or via hardware support. */ -volatile _Float16 two = 2.0F16; -volatile _Float16 three = 3.0F16; -volatile _Float16 result_add, result_sub, result_mul, result_div; - -int -main (int argc, char *argv[]) -{ - result_add = three + two; - result_sub = three - two; - result_mul = three * two; - result_div = three / two; - - if (((double)result_add) != 5.0) - abort (); - - if (((double)result_sub) != 1.0) - abort (); - - if (((double)result_mul) != 6.0) - abort (); - - if (((double)result_div) != 1.5) - abort (); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/powerpc/float16-2.c b/gcc/testsuite/gcc.target/powerpc/float16-2.c deleted file mode 100644 index 27df6dbaf23f..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/float16-2.c +++ /dev/null @@ -1,73 +0,0 @@ -/* { dg-do run } */ -/* { dg-require-effective-target ppc_float16_hw } */ -/* { dg-options "-mfloat16 -O2" } */ - -#include <stdlib.h> - -/* On a power10/power11 system, test whether we can do _Float16 calculations - with both software emulation (i.e. running the code with -mcpu=power8) and - hardware conversions (i.e. with -mcpu=power9, -mcpu=power10 or - -mcpu=power11). - - Power9 supports the XSCVHPDP and XSCVDPHP instructions that convert between - a scalar _Float16 and a scalar double. */ - -extern void do_power9 (void) __attribute__ ((noinline,target("cpu=power9"))); -extern void do_power8 (void) __attribute__ ((noinline,target("cpu=power8"))); - -volatile __bfloat16 two = 2.0; -volatile __bfloat16 three = 3.0; -volatile __bfloat16 p8_add, p8_sub, p8_mul, p8_div; -volatile __bfloat16 p10_add, p10_sub, p10_mul, p10_div; - -void -do_power8 (void) -{ - p8_add = three + two; - p8_sub = three - two; - p8_mul = three * two; - p8_div = three / two; -} - -void -do_power10 (void) -{ - p10_add = three + two; - p10_sub = three - two; - p10_mul = three * two; - p10_div = three / two; -} - -int -main (int argc, char *argv[]) -{ - do_power8 (); - - if (((double)p8_add) != 5.0) - abort (); - - if (((double)p8_sub) != 1.0) - abort (); - - if (((double)p8_mul) != 6.0) - abort (); - - if (((double)p8_div) != 1.5) - abort (); - - do_power10 (); - - if (((double)p10_add) != 5.0) - abort (); - - if (((double)p10_sub) != 1.0) - abort (); - - if (((double)p10_mul) != 6.0) - abort (); - - if (((double)p10_div) != 1.5) - abort (); - - return 0; -} diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index cb20b92a60c4..b1c0ed740c90 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3579,140 +3579,6 @@ proc check_ppc_recip_hw_available { } { }] } -# Return true if the PowerPC has hardware support for doing _Float16 -# conversions -proc check_ppc_float16_hw_available { } { - return [check_cached_effective_target ppc_float16_hw_available { - # Some simulators may not support XSCVHPDP - # For now, disable on Darwin - if { [istarget powerpc-*-eabi] || [istarget *-*-darwin*]} { - expr 0 - } else { - set options "-mfloat16" - check_runtime_nocache ppc_float16_hw_available { - extern void abort (void); - volatile _Float16 x = 3.0F16; - volatile union { - _Float16 five_f16; - unsigned short five_us; - } u = { 5.0F16 }; - int main() - { - double y; - asm ("xscvhpdp %x0,%x1" : "=wa" (y) : "wa" (x)); - if (y != 3.0) - abort (); - if (u.five_us != 0x4500) - abort (); - return 0; - } - } $options - } - }] -} - -# Return true if the PowerPC can do _Float16 calculations via either -# software or hardware support. -proc check_ppc_float16_runtime_available { } { - return [check_cached_effective_target ppc_float16_runtime_available { - # Some simulators may not support XSCVHPDP - # For now, disable on Darwin - if { [istarget powerpc-*-eabi] || [istarget *-*-darwin*]} { - expr 0 - } else { - set options "-mfloat16" - check_runtime_nocache ppc_float16_runtime_available { - extern void abort (void); - volatile _Float16 x = 3.0F16; - volatile _Float16 y = 4.0F16; - volatile _Float16 z; - volatile union { - _Float16 five_f16; - unsigned short five_us; - } u = { 5.0F16 }; - int main() - { - z = x + y; - if (((double)z) != 7.0) - abort (); - if (u.five_us != 0x4500) - abort (); - return 0; - } - } $options - } - }] -} - -# Return true if the PowerPC has hardware support for doing __bfloat16 -# conversions -proc check_ppc_bfloat16_hw_available { } { - return [check_cached_effective_target ppc_bfloat16_hw_available { - # Some simulators may not support XVCVBF16SPN/XVADDSP - # For now, disable on Darwin - if { [istarget powerpc-*-eabi] || [istarget *-*-darwin*]} { - expr 0 - } else { - set options "-mfloat16" - check_runtime_nocache ppc_float16_hw_available { - extern void abort (void); - typedef __bfloat16 vbf16 __attribute__ ((vector_size (16))); - volatile vbf16 x = { 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 }; - volatile vector float y = { 2.0f, 2.0f, 2.0f, 2.0f }; - volatile vector float z; - volatile vector float r; - volatile union { - __bfloat16 five_bf16; - unsigned short five_us; - } u = { 5.0 }; - int main() - { - asm ("xvcvbf16spn %x0,%x1" : "=wa" (z) : "wa" (x)); - r = y + z; - if (r[0] != 3.0 || r[1] != 3.0 || r[2] != 3.0 || r[3] != 3.0) - abort (); - if (u.five_us != 0x40a0) - abort (); - return 0; - } - } $options - } - }] -} - -# Return true if the PowerPC can do __bfloat16 calculations via either -# software or hardware support. -proc check_ppc_bfloat16_runtime_available { } { - return [check_cached_effective_target ppc_bfloat16_runtime_available { - # Some simulators may not support XVCVBF16SPN - # For now, disable on Darwin - if { [istarget powerpc-*-eabi] || [istarget *-*-darwin*]} { - expr 0 - } else { - set options "-mfloat16" - check_runtime_nocache ppc_bfloat16_runtime_available { - extern void abort (void); - volatile __bfloat16 x = 3.0; - volatile __bfloat16 y = 4.0; - volatile __bfloat16 z; - volatile union { - __bfloat16 five_bf16; - unsigned short five_us; - } u = { 5.0 }; - int main() - { - z = x + y; - if (((double)z) != 7.0) - abort (); - if (u.five_us != 0x40a0) - abort (); - return 0; - } - } $options - } - }] -} - # Return 1 if the target supports executing AltiVec and Cell PPU # instructions, 0 otherwise. Cache the result. @@ -10707,10 +10573,6 @@ proc is-effective-target { arg } { "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] } "ppc_cpu_supports_hw" { set selected [check_ppc_cpu_supports_hw_available] } "ppc_mma_hw" { set selected [check_ppc_mma_hw_available] } - "ppc_float16_hw" { set selected [check_ppc_float16_hw_available] } - "ppc_float16_runtime" { set selected [check_ppc_float16_runtime_available] } - "ppc_bfloat16_hw" { set selected [check_ppc_bfloat16_hw_available] } - "ppc_bfloat16_runtime" { set selected [check_ppc_bfloat16_runtime_available] } "dfp_hw" { set selected [check_dfp_hw_available] } "htm_hw" { set selected [check_htm_hw_available] } "named_sections" { set selected [check_named_sections_available] }
