https://gcc.gnu.org/g:20b671e685e690477efb1da2450a9938b760f279
commit r16-6158-g20b671e685e690477efb1da2450a9938b760f279 Author: Claudiu Zissulescu <[email protected]> Date: Wed Aug 27 17:38:49 2025 +0300 target-insns.def: (compose_tag) New pattern. Add a new target instruction used by hardware-assisted sanitizers on architectures providing memory-tagging instructions. This instruction is used to compute assign tags at a fixed offset from a tagged address base. For example, in AArch64 case, this pattern instantiate `addg` instruction. gcc/ * target-insns.def (compose_tag): New target instruction. * doc/md.texi (compose_tag): Add documentation. Signed-off-by: Claudiu Zissulescu <[email protected]> Diff: --- gcc/doc/md.texi | 5 +++++ gcc/target-insns.def | 1 + 2 files changed, 6 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 79588762fd38..ced69e741d01 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -8684,6 +8684,11 @@ This pattern tags an object that begins at the address specified by operand 0, has the byte size indicated by the operand 2, and uses the tag from operand 1. +@cindex @code{compose_tag} instruction pattern +This pattern composes a tagged address specified by operand 1 with +mode @code{ptr_mode}, with an integer operand 2 representing the tag +offset. It returns the result in operand 0 with mode @code{ptr_mode}. + @cindex @code{clear_cache} instruction pattern @item @samp{clear_cache} This pattern, if defined, flushes the instruction cache for a region of diff --git a/gcc/target-insns.def b/gcc/target-insns.def index 16e1d8cf565f..bfdc078378f0 100644 --- a/gcc/target-insns.def +++ b/gcc/target-insns.def @@ -47,6 +47,7 @@ DEF_TARGET_INSN (call_value_pop, (rtx x0, rtx x1, rtx opt2, rtx opt3, DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)) DEF_TARGET_INSN (check_stack, (rtx x0)) DEF_TARGET_INSN (clear_cache, (rtx x0, rtx x1)) +DEF_TARGET_INSN (compose_tag, (rtx x0, rtx x1, rtx x2)) DEF_TARGET_INSN (doloop_begin, (rtx x0, rtx x1)) DEF_TARGET_INSN (doloop_end, (rtx x0, rtx x1)) DEF_TARGET_INSN (eh_return, (rtx x0))
