https://gcc.gnu.org/g:3d836893900f0048fb5769767013d1af19041eae
commit 3d836893900f0048fb5769767013d1af19041eae Author: Jeff Law <[email protected]> Date: Thu Jan 8 21:14:18 2026 -0700 [RISC-V] Clamp long reservations to 7c So I've been noticing the cycle time for a native build/test on the Pioneer and BPI rising over the last many months. I've suspected a pain point is likely genautomata due to long reservations in the DFAs. Trying to describe a 30+ cycle bubble in the pipeline just isn't useful and causes the DFA to blow up. This is time to build insn-automata.cc using an optimized genautomata using my skylake server cross compiling to riscv64. The baseline is what we have today. Then I clamped the reservations (but not the latency) to 7c. 7c is arbitrary, but known not to blow up the DFA. I fixed the BPI first, then the Andes 23 and so-on. Baseline 52s BPI 52s Andes-23 45s Andes-25 16s Andes-45 16s Generic 15s Mips-8700 15s Sifive-7 13s Final 13s That's a significant improvement, though I probably wouldn't go forward with just that improvement. It's less than a minute and skylake systems aren't exactly new anymore... Let's try that with an unoptimized genautomata. I often build that way when debugging. Baseline 343s Final 79s So that's saving ~4m on my skylake server for a common build. Given I use ccache, that 4m is often a significant amount of the build time. So this feels like a better motivating example. But I'm really after bringing down bootstrap cycle times on the BPI and Pioneer. So let's see what the BPI does. For an optimized genautomata we get (not testing all the intermediate steps): Baseline 310s Final: 110s Not bad. And if we look at unoptimized genautomata: Baseline: 2196s Final: 553s Now we can see why bootstrap times have crept up meaningfully. That's ~27 minutes out of a 9hr bootstrap time on the BPI (pure bootstrap, no testing). The effect is more pronounced on the Pioneer where the improvement is 30+ minutes on a 4hr bootstrap time (each core is slower, but there's 8x as many cores). Tested on riscv{32,64}-elf and bootstrapped on the Pioneer (regression testing in progress). I'll wait for pre-commit CI to do its thing. gcc/ * config/riscv/andes-23-series.md: Clamp reservations to 7c. * config/riscv/andes-25-series.md: Likewise. * config/riscv/andes-45-series.md: Likewise. * config/riscv/generic.md: Likewise. * config/riscv/mips-p8700.md: Likewise. * config/riscv/sifive-7.md: Likewise. * config/riscv/spacemit-x60.md: Likewise. (cherry picked from commit 8265192910c8b05162ae7672d8fac85c1639c0c5) Diff: --- gcc/config/riscv/andes-23-series.md | 8 ++++---- gcc/config/riscv/andes-25-series.md | 12 ++++++------ gcc/config/riscv/andes-45-series.md | 12 ++++++------ gcc/config/riscv/generic.md | 10 +++++----- gcc/config/riscv/mips-p8700.md | 2 +- gcc/config/riscv/sifive-7.md | 30 +++++++++++++++--------------- gcc/config/riscv/spacemit-x60.md | 20 ++++++++++---------- 7 files changed, 47 insertions(+), 47 deletions(-) diff --git a/gcc/config/riscv/andes-23-series.md b/gcc/config/riscv/andes-23-series.md index 8e19e05da17d..a1bb3235903f 100644 --- a/gcc/config/riscv/andes-23-series.md +++ b/gcc/config/riscv/andes-23-series.md @@ -72,13 +72,13 @@ (and (eq_attr "tune" "andes_23_series") (and (eq_attr "type" "idiv") (eq_attr "mode" "SI"))) - "andes_23_pipe_unify, andes_23_mdu* 34") + "andes_23_pipe_unify, andes_23_mdu* 6") (define_insn_reservation "andes_23_idivdi" 35 (and (eq_attr "tune" "andes_23_series") (and (eq_attr "type" "idiv") (eq_attr "mode" "DI"))) - "andes_23_pipe_unify, andes_23_mdu* 34") + "andes_23_pipe_unify, andes_23_mdu* 6") (define_insn_reservation "andes_23_xfer" 1 (and (eq_attr "tune" "andes_23_series") @@ -103,12 +103,12 @@ (define_insn_reservation "andes_23_fpu_div" 33 (and (eq_attr "tune" "andes_23_series") (eq_attr "type" "fdiv")) - "andes_23_pipe_unify, andes_23_fpu*33") + "andes_23_pipe_unify, andes_23_fpu*6") (define_insn_reservation "andes_23_fpu_sqrt" 33 (and (eq_attr "tune" "andes_23_series") (eq_attr "type" "fsqrt")) - "andes_23_pipe_unify, andes_23_fpu*33") + "andes_23_pipe_unify, andes_23_fpu*6") (define_insn_reservation "andes_23_fpu_move" 2 (and (eq_attr "tune" "andes_23_series") diff --git a/gcc/config/riscv/andes-25-series.md b/gcc/config/riscv/andes-25-series.md index ef1a926de864..bb22ffbc2467 100644 --- a/gcc/config/riscv/andes-25-series.md +++ b/gcc/config/riscv/andes-25-series.md @@ -88,13 +88,13 @@ (and (eq_attr "tune" "andes_25_series") (and (eq_attr "type" "idiv") (eq_attr "mode" "SI"))) - "andes_25_pipe, andes_25_mdu * 34") + "andes_25_pipe, andes_25_mdu * 6") (define_insn_reservation "andes_25_idivdi" 70 (and (eq_attr "tune" "andes_25_series") (and (eq_attr "type" "idiv") (eq_attr "mode" "DI"))) - "andes_25_pipe, andes_25_mdu * 66") + "andes_25_pipe, andes_25_mdu * 6") (define_insn_reservation "andes_25_xfer" 1 (and (eq_attr "tune" "andes_25_series") @@ -119,12 +119,12 @@ (define_insn_reservation "andes_25_fpu_div" 33 (and (eq_attr "tune" "andes_25_series") (eq_attr "type" "fdiv")) - "andes_25_fpu_arith, andes_25_fpu_eu * 27") + "andes_25_fpu_arith, andes_25_fpu_eu * 6") (define_insn_reservation "andes_25_fpu_sqrt" 33 (and (eq_attr "tune" "andes_25_series") (eq_attr "type" "fsqrt")) - "andes_25_fpu_arith, andes_25_fpu_eu * 27") + "andes_25_fpu_arith, andes_25_fpu_eu * 6") (define_insn_reservation "andes_25_fpu_move" 3 (and (eq_attr "tune" "andes_25_series") @@ -234,7 +234,7 @@ (define_insn_reservation "andes_25_vidiv" 35 (and (eq_attr "tune" "andes_25_series") (eq_attr "type" "vidiv")) - "andes_25_vpu_pipe + andes_25_vpu_div*34") + "andes_25_vpu_pipe + andes_25_vpu_div*7") (define_insn_reservation "andes_25_vmask_2" 2 (eq_attr "type" "vmalu,vmsfs") @@ -264,7 +264,7 @@ (define_insn_reservation "andes_25_vfdiv" 39 (and (eq_attr "tune" "andes_25_series") (eq_attr "type" "vfdiv,vfsqrt")) - "andes_25_vpu_pipe + andes_25_vpu_div*19") + "andes_25_vpu_pipe + andes_25_vpu_div*7") (define_insn_reservation "andes_25_vfmis" 2 (and (eq_attr "tune" "andes_25_series") diff --git a/gcc/config/riscv/andes-45-series.md b/gcc/config/riscv/andes-45-series.md index cca9b3fba110..06de2584b8bd 100644 --- a/gcc/config/riscv/andes-45-series.md +++ b/gcc/config/riscv/andes-45-series.md @@ -145,15 +145,15 @@ (eq_attr "mode" "DF"))) "(andes_45_pipe0 | andes_45_pipe1) + andes_45_fpu_fmac + andes_45_fpu_fmv + andes_45_fpu_fmis") -(define_insn_reservation "andes_45_fpu_div" 33 +(define_insn_reservation "andes_45_fpu_div" 7 (and (eq_attr "tune" "andes_45_series") (eq_attr "type" "fdiv")) - "andes_45_pipe0 + andes_45_fpu_fdiv | andes_45_pipe1 + andes_45_fpu_fdiv, andes_45_fpu_fdiv * 27") + "andes_45_pipe0 + andes_45_fpu_fdiv | andes_45_pipe1 + andes_45_fpu_fdiv, andes_45_fpu_fdiv * 6") -(define_insn_reservation "andes_45_fpu_sqrt" 33 +(define_insn_reservation "andes_45_fpu_sqrt" 7 (and (eq_attr "tune" "andes_45_series") (eq_attr "type" "fsqrt")) - "andes_45_pipe0 + andes_45_fpu_fdiv | andes_45_pipe1 + andes_45_fpu_fdiv, andes_45_fpu_fdiv * 27") + "andes_45_pipe0 + andes_45_fpu_fdiv | andes_45_pipe1 + andes_45_fpu_fdiv, andes_45_fpu_fdiv * 6") (define_insn_reservation "andes_45_fpu_move" 1 (and (eq_attr "tune" "andes_45_series") @@ -231,10 +231,10 @@ (eq_attr "type" "vimul,viwmul,vsmul")) "andes_45_vpu_pipe + andes_45_vpu_mac") -(define_insn_reservation "andes_45_vpu_div" 36 +(define_insn_reservation "andes_45_vpu_div" 7 (and (eq_attr "tune" "andes_45_series") (eq_attr "type" "vidiv")) - "andes_45_vpu_pipe + andes_45_vpu_div * 35") + "andes_45_vpu_pipe + andes_45_vpu_div * 7") (define_insn_reservation "andes_45_vpu_madd" 4 (and (eq_attr "tune" "andes_45_series") diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index 9d1d3588d39a..c50a978a3df4 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -60,19 +60,19 @@ (define_insn_reservation "generic_imul" 10 (and (eq_attr "tune" "generic") (eq_attr "type" "imul,clmul,cpop")) - "imuldiv*10") + "imuldiv*7") (define_insn_reservation "generic_idivsi" 34 (and (eq_attr "tune" "generic") (and (eq_attr "type" "idiv") (eq_attr "mode" "SI"))) - "imuldiv*34") + "imuldiv*7") (define_insn_reservation "generic_idivdi" 66 (and (eq_attr "tune" "generic") (and (eq_attr "type" "idiv") (eq_attr "mode" "DI"))) - "imuldiv*66") + "imuldiv*7") (define_insn_reservation "generic_fmul_half" 5 (and (eq_attr "tune" "generic") @@ -95,10 +95,10 @@ (define_insn_reservation "generic_fdiv" 20 (and (eq_attr "tune" "generic") (eq_attr "type" "fdiv")) - "fdivsqrt*20") + "fdivsqrt*7") (define_insn_reservation "generic_fsqrt" 25 (and (eq_attr "tune" "generic") (eq_attr "type" "fsqrt")) - "fdivsqrt*25") + "fdivsqrt*7") diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md index fac9abbb198b..e46fc91f9112 100644 --- a/gcc/config/riscv/mips-p8700.md +++ b/gcc/config/riscv/mips-p8700.md @@ -82,7 +82,7 @@ (define_insn_reservation "mips_p8700_fpu_div" 17 (and (eq_attr "tune" "mips_p8700") (eq_attr "type" "fdiv,fsqrt")) - "mips_p8700_fpu_long, mips_p8700_fpu_apu*17") + "mips_p8700_fpu_long, mips_p8700_fpu_apu*6") (define_insn_reservation "mips_p8700_fpu_fcvt" 4 (and (eq_attr "tune" "mips_p8700") diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md index a04b80bff04d..8db388901a00 100644 --- a/gcc/config/riscv/sifive-7.md +++ b/gcc/config/riscv/sifive-7.md @@ -63,7 +63,7 @@ (define_insn_reservation "sifive_7_div" 16 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "idiv")) - "sifive_7_B,sifive_7_idiv*15") + "sifive_7_B,sifive_7_idiv*6") (define_insn_reservation "sifive_7_alu" 2 (and (eq_attr "tune" "sifive_7") @@ -108,19 +108,19 @@ (and (eq_attr "tune" "sifive_7") (eq_attr "type" "fdiv,fsqrt") (eq_attr "mode" "HF")) - "sifive_7_B,sifive_7_fpu*13") + "sifive_7_B,sifive_7_fpu*6") (define_insn_reservation "sifive_7_fdiv_s" 27 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "fdiv,fsqrt") (eq_attr "mode" "SF")) - "sifive_7_B,sifive_7_fpu*26") + "sifive_7_B,sifive_7_fpu*6") (define_insn_reservation "sifive_7_fdiv_d" 56 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "fdiv,fsqrt") (eq_attr "mode" "DF")) - "sifive_7_B,sifive_7_fpu*55") + "sifive_7_B,sifive_7_fpu*6") (define_insn_reservation "sifive_7_i2f" 3 (and (eq_attr "tune" "sifive_7") @@ -216,22 +216,22 @@ (define_insn_reservation "sifive_7_vec_iwalu" 8 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "viwalu,viwmul,viwmuladd,vnshift,vwsll")) - "sifive_7_vcq,sifive_7_va*7") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_div" 16 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vidiv,vfdiv")) - "sifive_7_vcq,sifive_7_va*15") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_fixed_point" 8 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vsalu,vaalu,vsmul,vsshift")) - "sifive_7_vcq,sifive_7_va*7") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_narrow_fixed_point" 8 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vnclip")) - "sifive_7_vcq,sifive_7_va*7") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_fsimple" 4 (and (eq_attr "tune" "sifive_7") @@ -242,7 +242,7 @@ (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vfalu,vfmul,vfmuladd,vfrecp, vfcvtitof,vfcvtftoi,vfmerge,vfmov,vfsgnj")) - "sifive_7_vcq,sifive_7_va*7") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_fcmp" 4 (and (eq_attr "tune" "sifive_7") @@ -252,7 +252,7 @@ (define_insn_reservation "sifive_7_vec_fsqrt_fdiv" 16 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vfsqrt,vfdiv")) - "sifive_7_vcq,sifive_7_va*15") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_fwalu" 8 (and (eq_attr "tune" "sifive_7") @@ -260,12 +260,12 @@ vfwcvtftoi,vfwcvtftof,vfwcvtbf16, vfncvtitof,vfncvtftoi,vfncvtftof,vfncvtbf16, sf_vfnrclip,sf_vqmacc")) - "sifive_7_vcq,sifive_7_va*7") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_red" 12 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vired,vfredu,vfredo,viwred,vfwredu,vfwredo")) - "sifive_7_vcq,sifive_7_va*11") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_mask" 4 (and (eq_attr "tune" "sifive_7") @@ -280,12 +280,12 @@ (define_insn_reservation "sifive_7_vec_gather" 8 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vgather")) - "sifive_7_vcq,sifive_7_va*7") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_compress" 16 (and (eq_attr "tune" "sifive_7") (eq_attr "type" "vcompress")) - "sifive_7_vcq,sifive_7_va*15") + "sifive_7_vcq,sifive_7_va*6") (define_insn_reservation "sifive_7_vec_slide" 4 (and (eq_attr "tune" "sifive_7") @@ -299,4 +299,4 @@ vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2, vaesz,vsha2ms,vsha2ch,vsha2cl, vsm4k,vsm4r,vsm3me,vsm3c,sf_vc,sf_vc_se")) - "sifive_7_vcq,sifive_7_va*15") + "sifive_7_vcq,sifive_7_va*6") diff --git a/gcc/config/riscv/spacemit-x60.md b/gcc/config/riscv/spacemit-x60.md index b4a5352ea572..dbf0c16f3d62 100644 --- a/gcc/config/riscv/spacemit-x60.md +++ b/gcc/config/riscv/spacemit-x60.md @@ -69,17 +69,17 @@ (eq_attr "type" "branch,jump,call,jalr,ret,trap,sfb_alu")) "spacemit_x60_alu0") -(define_insn_reservation "spacemit_x60_idivsi" 12 +(define_insn_reservation "spacemit_x60_idivsi" 7 (and (eq_attr "tune" "spacemit_x60") (and (eq_attr "type" "idiv") (eq_attr "mode" "SI"))) - "spacemit_x60_alu0*12") + "spacemit_x60_alu0*7") -(define_insn_reservation "spacemit_x60_idivdi" 20 +(define_insn_reservation "spacemit_x60_idivdi" 7 (and (eq_attr "tune" "spacemit_x60") (and (eq_attr "type" "idiv") (eq_attr "mode" "DI"))) - "spacemit_x60_alu0*20") + "spacemit_x60_alu0*7") (define_insn_reservation "spacemit_x60_imulsi" 3 (and (eq_attr "tune" "spacemit_x60") @@ -165,23 +165,23 @@ (eq_attr "mode" "DF"))) "spacemit_x60_fpalu") -(define_insn_reservation "spacemit_x60_fdiv_half" 12 +(define_insn_reservation "spacemit_x60_fdiv_half" 7 (and (eq_attr "tune" "spacemit_x60") (and (eq_attr "type" "fdiv,fsqrt") (eq_attr "mode" "HF"))) - "spacemit_x60_fdivsqrt*12") + "spacemit_x60_fdivsqrt*7") -(define_insn_reservation "spacemit_x60_fdiv_single" 15 +(define_insn_reservation "spacemit_x60_fdiv_single" 7 (and (eq_attr "tune" "spacemit_x60") (and (eq_attr "type" "fdiv,fsqrt") (eq_attr "mode" "SF"))) - "spacemit_x60_fdivsqrt*15") + "spacemit_x60_fdivsqrt*7") -(define_insn_reservation "spacemit_x60_fdiv_double" 22 +(define_insn_reservation "spacemit_x60_fdiv_double" 7 (and (eq_attr "tune" "spacemit_x60") (and (eq_attr "type" "fdiv,fsqrt") (eq_attr "mode" "DF"))) - "spacemit_x60_fdivsqrt*22") + "spacemit_x60_fdivsqrt*7") (define_insn_reservation "spacemi6_x60_dummy" 1 (and (eq_attr "tune" "spacemit_x60")
