https://gcc.gnu.org/g:efed253b3d6418b1e9eac658e7046e09dcc2a416
commit r16-6863-gefed253b3d6418b1e9eac658e7046e09dcc2a416 Author: Sandra Loosemore <[email protected]> Date: Wed Dec 31 16:28:38 2025 +0000 doc, rs6000: Clean up RS/6000 options documentation [PR122243] Similar to other patches in this series, the focus is on ensuring all options are either documented or marked "Undocumented", listed in both the options summary and detailed documentation, and both positive and negative forms have entries in the table of contents. gcc/ChangeLog PR other/122243 * config/rs6000/darwin.opt (Waltivec-long-deprecated): Mark as Undocumented. (faltivec, ffix-and-continue, findirect-data): Likewise. * config/rs6000/rs6000.opt (mvrsave): Likewise. * config/rs6000/sysv4.opt (mno-toc, mtoc, mno-traceback): Likewise. (mshlib, mnewlib): Likewise. * doc/invoke.texi (Option Summary) <RS/6000 and PowerPC Options>: Document only one form of each option. Add missing options. Correct whitespace. (RS/6000 and PowerPC Options): Separately document -mpowerpc-gpopt, -mpowerpc-gfxopt, -mpowerpc64, -mmfcrf, -mpopcntb, -mpopcntd, -mfprnd, -mcmpb, and -mhard-dfp and move their documentation after -mcpu=. Remove documentation for -mtoc which is unimplemented. Add missing @opindex entries. Minor copy-editing and whitespace fixes. Diff: --- gcc/config/rs6000/darwin.opt | 8 +- gcc/config/rs6000/rs6000.opt | 4 +- gcc/config/rs6000/sysv4.opt | 12 +- gcc/doc/invoke.texi | 275 +++++++++++++++++++++---------------------- 4 files changed, 145 insertions(+), 154 deletions(-) diff --git a/gcc/config/rs6000/darwin.opt b/gcc/config/rs6000/darwin.opt index 8e1f8f05e6c4..bc3344fc7301 100644 --- a/gcc/config/rs6000/darwin.opt +++ b/gcc/config/rs6000/darwin.opt @@ -20,18 +20,18 @@ ; <http://www.gnu.org/licenses/>. Waltivec-long-deprecated -Driver Alias(mwarn-altivec-long) +Driver Undocumented Alias(mwarn-altivec-long) faltivec -Driver +Driver Undocumented ; -ffix-and-continue and -findirect-data are for compatibility for old ; compilers. ffix-and-continue -Driver RejectNegative Alias(mfix-and-continue) +Driver Undocumented RejectNegative Alias(mfix-and-continue) findirect-data -Driver RejectNegative Alias(mfix-and-continue) +Driver Undocumented RejectNegative Alias(mfix-and-continue) m64 Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index fe93c366824c..2eeb45a4b71e 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -309,11 +309,11 @@ Target Var(TARGET_ALTIVEC_VRSAVE) Save Generate VRSAVE instructions when generating AltiVec code. mvrsave=no -Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead) +Target Undocumented RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead) Deprecated option. Use -mno-vrsave instead. mvrsave=yes -Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead) +Target Undocumented RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead) Deprecated option. Use -mvrsave instead. mblock-move-inline-limit= diff --git a/gcc/config/rs6000/sysv4.opt b/gcc/config/rs6000/sysv4.opt index 87d9d036937c..66b0de0ae43a 100644 --- a/gcc/config/rs6000/sysv4.opt +++ b/gcc/config/rs6000/sysv4.opt @@ -82,11 +82,11 @@ Produce big endian code. ;; FIXME: This does nothing. What should be done? mno-toc -Target RejectNegative +Target RejectNegative Undocumented No description yet. mtoc -Target RejectNegative +Target RejectNegative Undocumented No description yet. mprototype @@ -95,7 +95,7 @@ Assume all variable arg functions are prototyped. ;; FIXME: Does nothing. mno-traceback -Target RejectNegative +Target RejectNegative Undocumented No description yet. meabi @@ -136,8 +136,9 @@ memb Target RejectNegative Set the PPC_EMB bit in the ELF flags header. +; Used in specs. mshlib -Target RejectNegative +Target Undocumented RejectNegative No description yet. m64 @@ -148,8 +149,9 @@ m32 Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags) Generate 32-bit code. +; Used in specs. mnewlib -Target RejectNegative +Target Undocumented RejectNegative No description yet. msecure-plt diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 42aed3eb0b4f..5003f3e96249 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1347,23 +1347,18 @@ See RS/6000 and PowerPC Options. -mtune=@var{cpu-type} -mcmodel=@var{code-model} -mpowerpc64 --maltivec -mno-altivec --mpowerpc-gpopt -mno-powerpc-gpopt --mpowerpc-gfxopt -mno-powerpc-gfxopt --mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd --mfprnd -mno-fprnd --mcmpb -mno-cmpb -mhard-dfp -mno-hard-dfp --mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc --m64 -m32 -mxl-compat -mno-xl-compat -mpe +-maltivec +-mpowerpc-gpopt -mpowerpc-gfxopt -mmfcrf -mpopcntb -mpopcntd +-mfprnd -mcmpb -mhard-dfp +-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc +-maix64 -maix32 -m64 -m32 -mxl-compat -mpe -malign-power -malign-natural --msoft-float -mhard-float -mmultiple -mno-multiple --mupdate -mno-update --mavoid-indexed-addresses -mno-avoid-indexed-addresses --mfused-madd -mno-fused-madd -mbit-align -mno-bit-align --mstrict-align -mno-strict-align -mrelocatable --mno-relocatable -mrelocatable-lib -mno-relocatable-lib --mtoc -mno-toc -mlittle -mlittle-endian -mbig -mbig-endian --mdynamic-no-pic -mswdiv -msingle-pic-base +-msoft-float -mhard-float -mmultiple -mupdate +-mavoid-indexed-addresses +-mfused-madd -mbit-align +-mstrict-align -mrelocatable -mrelocatable-lib +-mlittle -mlittle-endian -mbig -mbig-endian +-mdynamic-no-pic -msingle-pic-base -mprioritize-restricted-insns=@var{priority} -msched-costly-dep=@var{dependence_type} -minsert-sched-nops=@var{scheme} @@ -1374,35 +1369,25 @@ See RS/6000 and PowerPC Options. -maix-struct-return -msvr4-struct-return -mabi=@var{abi-type} -msecure-plt -mbss-plt -msplit-patch-nops --mlongcall -mno-longcall -mpltseq -mno-pltseq +-mregnames -mlongcall -mpltseq -mtls-markers -mblock-move-inline-limit=@var{num} -mblock-compare-inline-limit=@var{num} -mblock-compare-inline-loop-limit=@var{num} --mno-block-ops-unaligned-vsx +-mblock-ops-unaligned-vsx -mstring-compare-inline-limit=@var{num} --misel -mno-isel --mvrsave -mno-vrsave --mmulhw -mno-mulhw --mdlmzb -mno-dlmzb --mprototype -mno-prototype --msim -mmvme -mads -myellowknife -memb -msdata +-misel -mvsx -mvrsave -mmulhw -mdlmzb -mprototype +-msim -mmvme -mads -myellowknife -memb -meabi -msdata -msdata=@var{opt} -mreadonly-in-sdata -mvxworks -G @var{num} -mrecip -mrecip=@var{opt} -mno-recip -mrecip-precision --mno-recip-precision --mveclibabi=@var{type} -mfriz -mno-friz --mpointers-to-nested-functions -mno-pointers-to-nested-functions --msave-toc-indirect -mno-save-toc-indirect --mpower8-fusion -mno-mpower8-fusion --mcrypto -mno-crypto -mhtm -mno-htm --mquad-memory -mno-quad-memory --mquad-memory-atomic -mno-quad-memory-atomic --mcompat-align-parm -mno-compat-align-parm --mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware --mgnu-attribute -mno-gnu-attribute --mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} --mstack-protector-guard-offset=@var{offset} -mprefixed -mno-prefixed --mpcrel -mno-pcrel -mmma -mno-mmma -mrop-protect -mno-rop-protect --mprivileged -mno-privileged} +-mveclibabi=@var{type} -mfriz +-mpointers-to-nested-functions -msave-toc-indirect -mpower8-fusion +-mcrypto -mhtm -mquad-memory -mquad-memory-atomic +-mcompat-align-parm +-mfloat128 -mfloat128-hardware +-mgnu-attribute +-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} +-mstack-protector-guard-offset=@var{offset} -mprefixed +-mpcrel -mmma -mrop-protect -mprivileged} @emph{RX Options} (@ref{RX Options}) @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu @@ -32555,84 +32540,8 @@ operation or it calls another function. @cindex IBM RS/6000 and PowerPC Options These @samp{-m} options are defined for the IBM RS/6000 and PowerPC: -@table @gcctabopt -@item -mpowerpc-gpopt -@itemx -mno-powerpc-gpopt -@itemx -mpowerpc-gfxopt -@itemx -mno-powerpc-gfxopt -@need 800 -@itemx -mpowerpc64 -@itemx -mno-powerpc64 -@itemx -mmfcrf -@itemx -mno-mfcrf -@itemx -mpopcntb -@itemx -mno-popcntb -@itemx -mpopcntd -@itemx -mno-popcntd -@itemx -mfprnd -@itemx -mno-fprnd -@need 800 -@opindex mpowerpc-gpopt -@opindex mno-powerpc-gpopt -@opindex mpowerpc-gfxopt -@opindex mno-powerpc-gfxopt -@opindex mpowerpc64 -@opindex mno-powerpc64 -@opindex mmfcrf -@opindex mno-mfcrf -@opindex mpopcntb -@opindex mno-popcntb -@opindex mpopcntd -@opindex mno-popcntd -@opindex mfprnd -@opindex mno-fprnd -@opindex mcmpb -@opindex mno-cmpb -@opindex mhard-dfp -@opindex mno-hard-dfp -@itemx -mcmpb -@itemx -mno-cmpb -@itemx -mhard-dfp -@itemx -mno-hard-dfp -You use these options to specify which instructions are available on the -processor you are using. The default value of these options is -determined when configuring GCC@. Specifying the -@option{-mcpu=@var{cpu_type}} overrides the specification of these -options. We recommend you use the @option{-mcpu=@var{cpu_type}} option -rather than the options listed above. - -Specifying @option{-mpowerpc-gpopt} allows -GCC to use the optional PowerPC architecture instructions in the -General Purpose group, including floating-point square root. Specifying -@option{-mpowerpc-gfxopt} allows GCC to -use the optional PowerPC architecture instructions in the Graphics -group, including floating-point select. - -The @option{-mmfcrf} option allows GCC to generate the move from -condition register field instruction implemented on the POWER4 -processor and other processors that support the PowerPC V2.01 -architecture. -The @option{-mpopcntb} option allows GCC to generate the popcount and -double-precision FP reciprocal estimate instruction implemented on the -POWER5 processor and other processors that support the PowerPC V2.02 -architecture. -The @option{-mpopcntd} option allows GCC to generate the popcount -instruction implemented on the POWER7 processor and other processors -that support the PowerPC V2.06 architecture. -The @option{-mfprnd} option allows GCC to generate the FP round to -integer instructions implemented on the POWER5+ processor and other -processors that support the PowerPC V2.03 architecture. -The @option{-mcmpb} option allows GCC to generate the compare bytes -instruction implemented on the POWER6 processor and other processors -that support the PowerPC V2.05 architecture. -The @option{-mhard-dfp} option allows GCC to generate the decimal -floating-point instructions implemented on some POWER processors. - -The @option{-mpowerpc64} option allows GCC to generate the additional -64-bit instructions that are found in the full PowerPC64 architecture -and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to -@option{-mno-powerpc64}. +@table @gcctabopt @opindex mcpu @item -mcpu=@var{cpu_type} Set architecture type, register usage, and @@ -32675,7 +32584,7 @@ following options: -mmulhw -mdlmzb -mmfpgpr -mvsx -mcrypto -mhtm -mpower8-fusion -mquad-memory -mquad-memory-atomic -mfloat128 --mfloat128-hardware -mprefixed -mpcrel -mmma +-mfloat128-hardware -mprefixed -mpcrel -mmma -mrop-protect} The particular options set for any particular CPU varies between @@ -32691,6 +32600,9 @@ AIX does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your environment. +In other cases, we recommend you use the @option{-mcpu=@var{cpu_type}} option +rather than the options that control generation of specific instructions. + @opindex mtune @item -mtune=@var{cpu_type} Set the instruction scheduling parameters for machine type @@ -32701,6 +32613,15 @@ values for @var{cpu_type} are used for @option{-mtune} as for architecture and registers set by @option{-mcpu}, but the scheduling parameters set by @option{-mtune}. +@opindex mpowerpc64 +@opindex mno-powerpc64 +@item -mpowerpc64 +@itemx -mno-powerpc64 +The @option{-mpowerpc64} option allows GCC to generate the additional +64-bit instructions that are found in the full PowerPC64 architecture +and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to +@option{-mno-powerpc64}. + @opindex mcmodel= @opindex mcmodel=small @item -mcmodel=small @@ -32737,6 +32658,71 @@ vector register when targeting a big-endian platform, and identifies the rightmost element in a vector register when targeting a little-endian platform. +@opindex mpowerpc-gpopt +@opindex mno-powerpc-gpopt +@item -mpowerpc-gpopt +@itemx -mno-powerpc-gpopt +Specifying @option{-mpowerpc-gpopt} allows +GCC to use the optional PowerPC architecture instructions in the +General Purpose group, including floating-point square root. Specifying + +@opindex mpowerpc-gfxopt +@opindex mno-powerpc-gfxopt +@item -mpowerpc-gfxopt +@itemx -mno-powerpc-gfxopt +@option{-mpowerpc-gfxopt} allows GCC to +use the optional PowerPC architecture instructions in the Graphics +group, including floating-point select. + +@opindex mmfcrf +@opindex mno-mfcrf +@item -mmfcrf +@itemx -mno-mfcrf +The @option{-mmfcrf} option allows GCC to generate the move from +condition register field instruction implemented on the POWER4 +processor and other processors that support the PowerPC V2.01 +architecture. + +@opindex mpopcntb +@opindex mno-popcntb +@item -mpopcntb +@itemx -mno-popcntb +The @option{-mpopcntb} option allows GCC to generate the popcount and +double-precision FP reciprocal estimate instruction implemented on the +POWER5 processor and other processors that support the PowerPC V2.02 +architecture. + +@opindex mpopcntd +@opindex mno-popcntd +@item -mpopcntd +@itemx -mno-popcntd +The @option{-mpopcntd} option allows GCC to generate the popcount +instruction implemented on the POWER7 processor and other processors +that support the PowerPC V2.06 architecture. + +@opindex mfprnd +@opindex mno-fprnd +@item -mfprnd +@itemx -mno-fprnd +The @option{-mfprnd} option allows GCC to generate the FP round to +integer instructions implemented on the POWER5+ processor and other +processors that support the PowerPC V2.03 architecture. + +@opindex mcmpb +@opindex mno-cmpb +@item -mcmpb +@itemx -mno-cmpb +The @option{-mcmpb} option allows GCC to generate the compare bytes +instruction implemented on the POWER6 processor and other processors +that support the PowerPC V2.05 architecture. + +@opindex mhard-dfp +@opindex mno-hard-dfp +@item -mhard-dfp +@itemx -mno-hard-dfp +The @option{-mhard-dfp} option allows GCC to generate the decimal +floating-point instructions implemented on some POWER processors. + @opindex mvrsave @opindex mno-vrsave @item -mvrsave @@ -32760,6 +32746,7 @@ sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option. @opindex msplit-patch-nops +@opindex mno-split-patch-nops @item -msplit-patch-nops When adding NOPs for a patchable area via the @option{-fpatchable-function-entry} option emit the ``before'' NOPs in front @@ -32840,11 +32827,11 @@ The default for @option{-mfloat128} is enabled on PowerPC Linux systems using the VSX instruction set, and disabled on other systems. If you use the ISA 3.0 instruction set (@option{-mcpu=power9}) on a -64-bit system, the IEEE 128-bit floating point support will also enable +64-bit system, the IEEE 128-bit floating point support also enables the generation of ISA 3.0 IEEE 128-bit floating point instructions. -Otherwise, if you do not specify to generate ISA 3.0 instructions or you -are targeting a 32-bit big endian system, IEEE 128-bit floating point -will be done with software emulation. +Otherwise, if you do not specify generation of ISA 3.0 instructions or you +are targeting a 32-bit big-endian system, IEEE 128-bit floating point +is handled with software emulation. @opindex mfloat128-hardware @opindex mno-float128-hardware @@ -32869,9 +32856,13 @@ pointer to 64 bits, and generates code for PowerPC64, as for @option{-mpowerpc64}. @opindex mfull-toc +@opindex mno-full-toc +@opindex mfp-in-toc @opindex mno-fp-in-toc +@opindex msum-in-toc @opindex mno-sum-in-toc @opindex mminimal-toc +@opindex mno-minimal-toc @item -mfull-toc @itemx -mno-fp-in-toc @itemx -mno-sum-in-toc @@ -32993,7 +32984,7 @@ signals may get corrupted data. @item -mavoid-indexed-addresses @itemx -mno-avoid-indexed-addresses Generate code that tries to avoid (not avoid) the use of indexed load -or store instructions. These instructions can incur a performance +or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targeting Power6 and disabled otherwise. @@ -33071,14 +33062,6 @@ alignment of @option{-mrelocatable}. Objects compiled with @option{-mrelocatable-lib} may be linked with objects compiled with any combination of the @option{-mrelocatable} options. -@opindex mno-toc -@opindex mtoc -@item -mno-toc -@itemx -mtoc -On System V.4 and embedded PowerPC systems do not (do) assume that -register 2 contains a pointer to a global area pointing to the addresses -used in the program. - @opindex mlittle @opindex mlittle-endian @item -mlittle @@ -33210,7 +33193,7 @@ OpenBSD operating system. @opindex mtraceback @item -mtraceback=@var{traceback_type} -Select the type of traceback table. Valid values for @var{traceback_type} +Select the type of traceback table. Valid values for @var{traceback_type} are @samp{full}, @samp{part}, and @samp{no}. @opindex maix-struct-return @@ -33397,24 +33380,24 @@ targets. The default value is target-specific. @item -mblock-compare-inline-limit=@var{num} Generate non-looping inline code for all block compares (such as calls to @code{memcmp} or structure compares) less than or equal to @var{num} -bytes. If @var{num} is 0, all inline expansion (non-loop and loop) of -block compare is disabled. The default value is target-specific. +bytes. If @var{num} is 0, all inline expansion (non-loop and loop) of +block compare is disabled. The default value is target-specific. @opindex mblock-compare-inline-loop-limit @item -mblock-compare-inline-loop-limit=@var{num} Generate an inline expansion using loop code for all block compares that are less than or equal to @var{num} bytes, but greater than the limit -for non-loop inline block compare expansion. If the block length is not -constant, at most @var{num} bytes will be compared before @code{memcmp} -is called to compare the remainder of the block. The default value is +for non-loop inline block compare expansion. If the block length is not +constant, at most @var{num} bytes are compared before @code{memcmp} +is called to compare the remainder of the block. The default value is target-specific. @opindex mstring-compare-inline-limit @item -mstring-compare-inline-limit=@var{num} Compare at most @var{num} string bytes with inline code. If the difference or end of string is not found at the -end of the inline compare a call to @code{strcmp} or @code{strncmp} will -take care of the rest of the comparison. The default is 64 bytes. +end of the inline compare, a call to @code{strcmp} or @code{strncmp} +takes care of the rest of the comparison. The default is 64 bytes. @opindex G @cindex smaller data references (PowerPC) @@ -33498,6 +33481,7 @@ TLS optimization, which in turn allows GCC to better schedule the sequence. @opindex mrecip +@opindex mno-recip @item -mrecip @itemx -mno-recip This option enables use of the reciprocal estimate and @@ -33558,6 +33542,7 @@ all of the reciprocal estimate instructions, except for the which handle the double-precision reciprocal square root calculations. @opindex mrecip-precision +@opindex mno-recip-precision @item -mrecip-precision @itemx -mno-recip-precision Assume (do not assume) that the reciprocal estimate instructions @@ -33593,6 +33578,7 @@ for power7. Both @option{-ftree-vectorize} and libraries must be specified at link time. @opindex mfriz +@opindex mno-friz @item -mfriz @itemx -mno-friz Generate (do not generate) the @code{friz} instruction when the @@ -33602,6 +33588,7 @@ point. The @code{friz} instruction does not return the same value if the floating-point number is too large to fit in an integer. @opindex mpointers-to-nested-functions +@opindex mno-pointers-to-nested-functions @item -mpointers-to-nested-functions @itemx -mno-pointers-to-nested-functions Generate (do not generate) code to load up the static chain register @@ -33615,6 +33602,7 @@ to functions compiled in other languages that use the static chain if you use @option{-mno-pointers-to-nested-functions}. @opindex msave-toc-indirect +@opindex mno-save-toc-indirect @item -msave-toc-indirect @itemx -mno-save-toc-indirect Generate (do not generate) code to save the TOC value in the reserved @@ -33624,6 +33612,7 @@ saved in the prologue, it is saved just before the call through the pointer. The @option{-mno-save-toc-indirect} option is the default. @opindex mcompat-align-parm +@opindex mno-compat-align-parm @item -mcompat-align-parm @itemx -mno-compat-align-parm Generate (do not generate) code to pass structure parameters with a @@ -33692,19 +33681,19 @@ optimization (@option{-fshrink-wrap}). @opindex mno-privileged @item -mprivileged @itemx -mno-privileged -Generate (do not generate) code that will run in privileged state. +Generate (do not generate) code that runs in privileged state. -@opindex block-ops-unaligned-vsx -@opindex no-block-ops-unaligned-vsx +@opindex mblock-ops-unaligned-vsx +@opindex mno-block-ops-unaligned-vsx @item -mblock-ops-unaligned-vsx @itemx -mno-block-ops-unaligned-vsx Generate (do not generate) unaligned vsx loads and stores for inline expansion of @code{memcpy} and @code{memmove}. @item --param rs6000-vect-unroll-limit= -The vectorizer will check with target information to determine whether it +The vectorizer checks with target information to determine whether it would be beneficial to unroll the main vectorized loop and by how much. This -parameter sets the upper bound of how much the vectorizer will unroll the main +parameter sets the upper bound of how much the vectorizer unrolls the main loop. The default value is four. @end table
