https://gcc.gnu.org/g:0c2b2d53879ee5519ae55955a57c7af847edd3f3
commit r16-6926-g0c2b2d53879ee5519ae55955a57c7af847edd3f3 Author: Alfie Richards <[email protected]> Date: Fri Jan 16 12:09:17 2026 +0000 aarch64: Update comment explaining code layout gcc/ChangeLog: * config/aarch64/aarch64.md: Update comment. * config/aarch64/aarch64-simd.md: Change comment to refer to aarch64.md. * config/aarch64/aarch64-sme.md: Likewise. * config/aarch64/aarch64-sve.md: Likewise. * config/aarch64/aarch64-sve2.md: Likewise. * config/aarch64/aarch64-sve-builtins.def: Update comment. * config/aarch64/aarch64-sve-builtins-base.def: Update to refer to aarch64-sve-builtins.def. * config/aarch64/aarch64-sve-builtins-sme.def: Likewise. * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. Diff: --- gcc/config/aarch64/aarch64-simd.md | 18 +------------ gcc/config/aarch64/aarch64-sme.md | 18 +------------ gcc/config/aarch64/aarch64-sve-builtins-base.def | 18 ++----------- gcc/config/aarch64/aarch64-sve-builtins-sme.def | 18 ++----------- gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 18 ++----------- gcc/config/aarch64/aarch64-sve-builtins.def | 34 +++++++++++++----------- gcc/config/aarch64/aarch64-sve.md | 18 +------------ gcc/config/aarch64/aarch64-sve2.md | 20 ++------------ gcc/config/aarch64/aarch64.md | 29 +++++++++++--------- 9 files changed, 45 insertions(+), 146 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0ef7339a40a7..505e8b1126fa 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -18,23 +18,7 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -;; Code organisation: -; -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are -;; a little blurry. -;; -;; Therefore code is organised by the following rough principles: -;; -;; - aarch64.md: For shared parts of the architecture (such as defining -;; registers and constants) and for instructions that operate on non-SIMD -;; registers. -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD -;; registers. -;; - aarch64-sve.md for SVE instructions that are pre SVE2. -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with -;; non-streaming mode. This usually means it uses the ZA or ZT register. -;; - aarch64-sve2.md for any scalable SIMD instruction that either is -;; streaming compatible, or theoretically could be later. +;; Code organization: See block comment at the top of aarch64.md. ;; The following define_subst rules are used to produce patterns representing ;; the implicit zeroing effect of 64-bit Advanced SIMD operations, in effect diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md index a2faa4b2bb73..72823e528ded 100644 --- a/gcc/config/aarch64/aarch64-sme.md +++ b/gcc/config/aarch64/aarch64-sme.md @@ -17,23 +17,7 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -;; Code organisation: -; -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are -;; a little blurry. -;; -;; Therefore code is organised by the following rough principles: -;; -;; - aarch64.md: For shared parts of the architecture (such as defining -;; registers and constants) and for instructions that operate on non-SIMD -;; registers. -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD -;; registers. -;; - aarch64-sve.md for SVE instructions that are pre SVE2. -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with -;; non-streaming mode. This usually means it uses the ZA or ZT register. -;; - aarch64-sve2.md for any scalable SIMD instruction that either is -;; streaming compatible, or theoretically could be later. +;; Code organization: See block comment at the top of aarch64.md. ;; The file is organised into the following sections (search for the full ;; line): diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.def b/gcc/config/aarch64/aarch64-sve-builtins-base.def index 0a3a7a0e144e..9914e060f4d5 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.def @@ -17,22 +17,8 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/* Code organisation: - - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get - a little blurry. - - Therefore code is organised by the following rough principles: - - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally - incompatible with non-streaming mode. This usually means it uses the ZA - or ZT register. - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode - intrinsic, but either is non-streaming compatible, or theoretically could - be later. - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. - - aarch64-sve-builtins.def for common data types and group definitions used - across all files. */ +/* Code organization: See block comment at the top of + aarch64-sve-builtins.def. */ #define REQUIRED_EXTENSIONS ssve (0) DEF_SVE_FUNCTION (svabd, binary_opt_n, all_arith, mxz) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def b/gcc/config/aarch64/aarch64-sve-builtins-sme.def index 9f126e8647a2..4feb47952874 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def @@ -17,22 +17,8 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/* Code organisation: - - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get - a little blurry. - - Therefore code is organised by the following rough principles: - - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally - incompatible with non-streaming mode. This usually means it uses the ZA - or ZT register. - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode - intrinsic, but either is non-streaming compatible, or theoretically could - be later. - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. - - aarch64-sve-builtins.def for common data types and group definitions used - across all files. */ +/* Code organization: See block comment at the top of + aarch64-sve-builtins.def. */ #ifndef DEF_SME_FUNCTION_GS #define DEF_SME_FUNCTION_GS(NAME, SHAPE, TYPES, GROUPS, PREDS) \ diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def index 8765021d951f..19249a588751 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def @@ -17,22 +17,8 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/* Code organisation: - - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get - a little blurry. - - Therefore code is organised by the following rough principles: - - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally - incompatible with non-streaming mode. This usually means it uses the ZA - or ZT register. - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode - intrinsic, but either is non-streaming compatible, or theoretically could - be later. - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. - - aarch64-sve-builtins.def for common data types and group definitions used - across all files. */ +/* Code organization: See block comment at the top of + aarch64-sve-builtins.def. */ #define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2, 0) DEF_SVE_FUNCTION (svaba, ternary_opt_n, all_integer, none) diff --git a/gcc/config/aarch64/aarch64-sve-builtins.def b/gcc/config/aarch64/aarch64-sve-builtins.def index ecd434bda35e..6ad257643b69 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.def +++ b/gcc/config/aarch64/aarch64-sve-builtins.def @@ -17,22 +17,24 @@ along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>. */ -/* Code organisation: - - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get - a little blurry. - - Therefore code is organised by the following rough principles: - - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally - incompatible with non-streaming mode. This usually means it uses the ZA - or ZT register. - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a streaming mode - intrinsic, but either is non-streaming compatible, or theoretically could - be later. - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. - - aarch64-sve-builtins.def for common data types and group definitions used - across all files. */ +/* Code organization: + + The taxonomic lines dividing intrinsics into sve, sve2, and sme are perhaps + a little non-obvious. + + The code is organized by the following rough principles: + + - aarch64-sve-builtins.def for common data types, groups, and other + supporting definitions used across all files. + - aarch64-sve-builtins-base.def for the baseline SVE intrinsics which predate + SVE2 and SME. + - aarch64-sve-builtins-sve2.def for any scalable SIMD intrinsic that is + enabled by an SVE2+ or SME+ extension and doesn't directly touch SME + state (such as ZA or ZT0) and only involves regular SVE vectors and + predicates. + - aarch64-sve-builtins-sme.def for any SME+ instinsic that is clearly + streaming mode only. This usually means it uses the ZA or ZT0 registers, + or other SME state. */ #ifndef DEF_SVE_MODE #define DEF_SVE_MODE(A, B, C, D) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index b77a04cd2d2d..846ed5c65d25 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -18,23 +18,7 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -;; Code organisation: -; -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are -;; a little blurry. -;; -;; Therefore code is organised by the following rough principles: -;; -;; - aarch64.md: For shared parts of the architecture (such as defining -;; registers and constants) and for instructions that operate on non-SIMD -;; registers. -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD -;; registers. -;; - aarch64-sve.md for SVE instructions that are pre SVE2. -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with -;; non-streaming mode. This usually means it uses the ZA or ZT register. -;; - aarch64-sve2.md for any scalable SIMD instruction that either is -;; streaming compatible, or theoretically could be later. +;; Code organization: See block comment at the top of aarch64.md. ;; The file is organised into the following sections (search for the full ;; line): diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index c63796542acb..4a2d2c1cb8ce 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -17,24 +17,8 @@ ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -; -;; Code organisation: -; -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are -;; a little blurry. -;; -;; Therefore code is organised by the following rough principles: -;; -;; - aarch64.md: For shared parts of the architecture (such as defining -;; registers and constants) and for instructions that operate on non-SIMD -;; registers. -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD -;; registers. -;; - aarch64-sve.md for SVE instructions that are pre SVE2. -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with -;; non-streaming mode. This usually means it uses the ZA or ZT register. -;; - aarch64-sve2.md for any scalable SIMD instruction that either is -;; streaming compatible, or theoretically could be later. + +;; Code organization: See block comment at the top of aarch64.md. ;; The file is organised into the following sections (search for the full ;; line): diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 58e57fd65a79..568e5814afc2 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -18,23 +18,26 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -;; Code organisation: +;; Code organization: ; -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are -;; a little blurry. +;; The taxonomic lines dividing instructions into aarch64, simd, sve, sve2, +;; and sme are perhaps a little non-obvious. ;; -;; Therefore code is organised by the following rough principles: +;; The code is organized by the following rough principles: ;; -;; - aarch64.md: For shared parts of the architecture (such as defining -;; registers and constants) and for instructions that operate on non-SIMD +;; - aarch64.md for shared parts of the architecture (such as defining +;; registers and constants) and for instructions that operate on +;; general-purpose registers. +;; - aarch64-simd.md for instructions that operate on Advanced SIMD ;; registers. -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD -;; registers. -;; - aarch64-sve.md for SVE instructions that are pre SVE2. -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible with -;; non-streaming mode. This usually means it uses the ZA or ZT register. -;; - aarch64-sve2.md for any scalable SIMD instruction that either is -;; streaming compatible, or theoretically could be later. +;; - aarch64-sve.md for the baseline SVE instructions which predate SVE2 and +;; SME. +;; - aarch64-sve2.md for any scalable SIMD instruction that is enabled by an +;; SVE2+ or SME+ extension and doesn't directly touch SME state (such as ZA, +;; or ZT0) and only involves regular SVE vectors and predicates. +;; - aarch64-sme.md for any scalable SIMD instruction that is clearly +;; streaming mode only. This usually means it uses the ZA or ZT0 register +;; or other SME state. ;; Register numbers (define_constants
