The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
8a04a2d7ea1f... RISC-V: Fix indexed store output template [PR123780].
It previously pointed to:
57a4a63e448c... RISC-V: Fix indexed store output template [PR123780].
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
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57a4a63... RISC-V: Fix indexed store output template [PR123780].
a007172... RISC-V: Add zvfbfmin to tt-ascalon-d8's extension list [PR1
2a5e3d1... forwprop: More nop-conversion handling [PR123731].
54aa936... RISC-V: Correct builtin registration order [PR123279].
45007c4... [PR rtl-optimization/123380] Avoid creating bogus SUBREG in
75319cb... [RISC-V][PR target/123626] Fix VXRM state after calls
f50a7c1... [RISC-V][PR rtl-optimization/121787] Work around bad cfglay
4a3f873... [PR target/113666] Simplify VEC_EXTRACT from a uniform vect
407246a... doc, riscv: Clean up documentation of RISC-V options [PR122
f15b6b6... vect: Make SELECT_VL a convert optab.
abea7aa... forwprop: Allow nop conversions for vector constructor.
aa2ba2e... forwprop: allow subvectors in simplify_vector_constructor (
631b6e1... forwprop: Check type conversion in pack/unpack [PR123117].
eccfa3e... [PR target/121778] Improving rotation detection
33cd3c0... [PR123092, LRA]: Reprocess insn after equivalence substitut
6691ab9... Fix RISC-V test after recent vectorizer changes
150b237... RISC-V: Enable the ZD constraint only when xmipscbop is ena
f8304a0... match: Add simplification of `(a*zero_one_valued_p) & b` if
9730e5b... ifcvt: Improve `cmp?a&b:a` to try with -1 [PR123312]
3b65b8e... forwprop: Fix type mismatch in vec constructor [PR123525].
b6964ea... if-conv: Prevent vector types in scalar cond reduction [PR1
7946cbe... rtlanal: Determine nonzero bits of popcount from operand [P
26434d8... VN: Fix VN ICE for large _BitInt types
745eafd... RISC-V: Add support for _BitInt [PR117581]
9ff3f5b... forwprop: Use ssizetype for mask [PR123414].
36311c4... RISC-V: Update tt-ascalon-d8's extension list [PR123492]
1d5ae46... ifcvt: Reject inner floating modes of a subreg for noce_try
6cfe2b0... [RISC-V] Clamp long reservations to 7c
8ddb9e7... RISC-V: -mrvv-max-lmul=conv-dynamic [PR122846].
6171760... [PATCH v3] match.pd: popcount(X & -X) -> -X != 0 [PR102486]
12bd187... [RISC-V] Restore inline expansion of block moves on RISC-V
947f37c... [PATCH v1 2/2] RISC-V: Add run test case for vwadd/vwsub wx
0aa58bc... [PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for an
30571a1... RISC-V: Adjust the asm check of vx_vf due to middle-end cha
1aff976... Vect: Adjust depth_limit of vec_slp_has_scalar_use from 2 t
5ff9546... Partially revert patch that made VXRM a global register on
265cf28... [PR target/123010] Simplify shift of sign extracted field t
15b24bc... [RISC-V][PR target/121485] Fix mode on Zvkned lmul extendin
39ebc29... [RISC-V][PR target/123318] Use a Pmode temporary for output
8f9212c... ifcvt: Allow non-comparisons against 0 in noce_try_cond_zer
1937864... ifcvt: Handle lowpart subregs if noce_emit_cmove fails in n
3cda579... ifcvt: cleanup if_info->cond usage in noce_try_cond_zero_ar
fd796cf... simplify-rtx: Fix up (ne (ior (ne x 0) y) 0) simplification
ee0b053... Revert "ifcvt: Move noce_try_cond_zero_arith last"
7fc51d6... [RISC-V][PR target/123283] Wrap naked REG operands with a U
02fd5c5... doc: make regenerate-opt-urls
1985fed... doc, riscv: Clean up RISC-V extensions documentation
3d83984... RISC-V: Add test for vec_duplicate + vmsleu.vv combine with
87cf1ed... RISC-V: Combine vec_duplicate + vmsleu.vv to vmsleu.vx on G
1c46218... ifcvt: Move noce_try_cond_zero_arith last
7b4ec20... ifcvt: Only allow scalar integral modes for noce_try_cond_z
406fc13... [committed][RISC-V][PR target/123274] Add missing condition
bf264db... [RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 s
76ee564... [RISC-V][PATCH] Adjust clmul latency in Spacemit X60 schedu
809650b... ifcvt: Fix noce_try_cond_zero_arith after get_base_reg chan
3a7f962... [RISC-V][V2] Improve spill code for RVV slightly to fix reg
9cd8c43... ifcvt: cond zero arith: handle subreg for shift count
8699592... ifcvt: cond zero arith: elide short forward branch for sign
878a13d... ifcvt: cond zero arith: re-expand output pattern [NFC]
a579f80... ifcvt: cond zero arith: factor out common noce_emit_czero e
4329b1e... ifcvt: cond zero arith: opencode helper noce_bbs_ok_for_con
abdeaf3... [RISC-V][V2] Improve spill code for RVV slightly to fix reg
635393b... RISC-V: Fix overflow check in interleave pattern [PR122970]
acbf8d2... RISC-V: Testsuite fixes.
0f67354... RISC-V: Generic vec_extract via subreg.
310c0eb... RISC-V: Add VLS modes to autovec iterators.
0626cd5... RISC-V: Rename vector-mode related functions.
1513dcb... RISC-V: Change gather/scatter iterators.
321ac9d... Fix various RISC-V testsuite regressions after volatile pat
46d9aba... [PATCH] RISC-V: Rename UPPERCAE_NAME to UPPERCASE_NAME
77369ad... RISC-V: Add test for vec_duplicate + vmslt.vv combine with
f618d17... RISC-V: Combine vec_duplicate + vmslt.vv to vmslt.vx on GR2
c9c6862... RISC-V: Regenerate opt urls.
890428b... RISC-V: -mmax-vectorization.
c1b028d... vect: Add vect-scalar-cost-multiplier for SLP.
14e3894... middle-end: Add new parameter to scale scalar loop costing
52d42df... RISC-V: Pragma target [PR115325].
8f6ca0d... RISC-V: Implement mask reduction.
7fc8878... [riscv] avoid auipc overflow with large offsets [PR91420]
e8e0b76... RISC-V: Add test for vec_duplicate + vmsltu.vv combine with
f7b73b8... RISC-V: Combine vec_duplicate + vmsltu.vv to vmsltu.vx on G
8e5098b... RISC-V: Remove unused placeholder_p parameter from add_func
4726ae3... [PATCH][PR target/122942] RISC-V: Add zifencei extension to
b51d8ba... riscv: RISCV backend, meet C++20
06e9cf4... RISC-V: Emit \n\t at the end of instruction instead of ;
8b3d6bc... RISC-V: Support --with-cpu
f7b4e1d... RISC-V: Add SpacemiT extension xsmtvdot
6702a6b... RISC-V: Run gen-riscv-ext-opt to regenerate riscv-ext.opt [
d32721f... RISC-V: Add Andes 45 series pipeline description.
e372b13... RISC-V: Add Andes 23 series pipeline description.
03046c0... RISC-V: Fix one typo result in pr121959-run-1 run failure
67104a8... Revert "[PATCH v3] RISC-V: Implement RISC-V profile macro s
792b2ef... RISC-V: Add testcase for unsigned scalar SAT_MUL form 7
97487b5... RISC-V: Add BF VLS modes and document iterators.
43eefa1... [PR rtl-optimization/122782] Fix out of range shift causing
b67f26c... [PR 122701] Emit fresh reg->reg copy rather than modifying
b61a5af... [PR118358, LRA]: Decrease pressure after issuing input relo
760abec... RISC-V: Add RTL pass to combine cm.popret with zero return
a3b46ff... [RISC-V] Fix trivial bootstrap failure on RISC-V
27fad66... RISC-V: Add flag to adjust mem inlining threshold
aa4314f... [RISC-V] Add cpu and tuning structures for spacemit-x60 des
3f5368b... RISC-V: Remove gather scale and offset handling.
57673f2... [PR rtl-optimization/122575] Fix mode on optimized IOR comp
1671089... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
6a009ef... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
4db053d... [RISC-V] Avoid most calls to gen_extend_insn
4fc97ca... [RISC-V] Drop scan-tests of marginal value
56fb774... RISC-V: Add missing member for andes_25_tune_info
7da7204... Handle shift-pairs in ext-dce for targets without zero/sign
a51a117... RISC-V: Add Andes 25 series pipeline description.
95d13d0... [RISC-V] Improve detection of packw
f1248f8... [RISC-V] Simplify riscv_extend_to_xmode_reg
edb1838... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
33e1f1d... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
73b4d4c... [RISC-V] Add testcase for shifted truthvalue
29d1486... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB
26f187f... RISC-V: Add test for vec_duplicate + vwmaccu.vv combine wit
c13e9e7... RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmac
97d982e... [RISC-V] Ignore useless zero-initialization in conditional
460fbe5... [RISC-V][PR 121136] Improve various tests which only need t
fb79fc5... RISC-V: testsuite: Fix pr119115.c.
6bd0acf... [PR rtl-optimization/122536] Fix guard against variable bit
c5ec331... RISC-V: Fix the ABI of empty unions and zero length array i
858f8f0... [RISC-V][PR tree-optimization/52345] Optimize testing multi
82eca05... [RISC-V] Expose sign extension for 32 bit rotates by consta
f71e858... gcc: Drop junk vim backup file
3903d79... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR
05df5aa... [RISC-V] Reorder ready queue slightly to avoid unnecessary
bc6238f... tree-optimization/122502 - avoid folding during imm use wal
8771b93... niter: Use ranger to query ctz range.
4b01526... [PATCH v2] RISC-V: avlprop: Scale AVL by subreg ratio [PR12
5f5d359... RISC-V: Clean up build warnings for VLS calling convention
e424d12... Skip riscv/rvv/xtheadvector/pr116593.C if not hostedlib
56d89a6... RISC-V: Add testsuite for fixed-length vector calling conve
5242b85... RISC-V: Add testsuite for fixed-length vector calling conve
5db7db2... RISC-V: Implement standard fixed-length vector calling conv
686be7a... [RISC-V][PR target/64345][PR tree-optimization/80770] Impro
5c02a3b... Increase NUM_ABI_IDS to support RISC-V VLS calling conventi
2601481... [PATCH v2] RISC-V: Fix moving data from V_REGS to GR_REGS b
16c6951... Fix minor RISC-V testsuite failure
8382236... Fix minor testsuite scan failures for RISC-V
5fc8a8b... RISC-V: Add testcase for unsigned scalar SAT_MUL form 6
95f0067... RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine
b40bb5c... [PATCH v3] RISC-V: Implement RISC-V profile macro support
f466b3f... [RISC-V][PR target/120811] Improving address reloads in LRA
235f02f... [PR target/119587] RISC-V: xtheadmemidx: Split slli.uw patt
6560d2f... [RISC-V] Improve subword atomic patterns in sync.md
98eb1f0... RISC-V: Add test for vec_duplicate + vwsubu.wv combine with
839cf9d... RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on G
c1d646c... RISC-V: Allow VLS types using up to LMUL 8
5f0fa69... [PATCH] RISC-V: Fix slide pattern recognition [PR122124]
164a09e... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
0e3e5fa... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
2ba8720... Fixup merge conflict
954bb2f... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
5d01786... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
fdcb73f... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
bc6c445... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
89dd103... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
c9bb431... [RISC-V][PR target/122106] Add missing predicate on crc exp
a062e47... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
a6406a6... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
027ffa6... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
8270e39... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
507d4b2... RISC-V: Improve slide patterns recognition
0460652... RISC-V: Only Save/Restore required registers for ILP32E/LP6
959cb14... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
fb35a01... RISC-V: Correct lmul estimation
6a09fd2... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
1ac9437... [PR tree-optimization/58727] Don't over-simplify constants`
b26c9ab... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
8de41a0... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
e4ad81d... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
bf3d8fd... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
e99a63c... RISC-V: Allow profiles input in '--with-arch' option.
9b804d8... RISC-V: Configure Profiles definitions in the definition fi
26586fd... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
251f1f9... Widening-Mul: Refine build_and_insert_cast when rhs is cast
c3c8ae3... RISC-V: Fix vendor intrinsic tests for disabled multilib co
9808669... RISC-V: Support vnclip idiom testcase [PR120378]
be747da... Match: Support SAT_TRUNC variant NARROW_CLIP
3ee81d1... [RISC-V] Adjust ABI specification in recently added Andes t
d52f37d... RISC-V: Suppress cross CC sibcall optimization from vector
4007f26... RISC-V: Add min/max patterns for ifcvt.
401b0f2... ifcvt: Clarify if_info.original_cost.
5986829... RISC-V: Fix can_find_related_mode_p for VLS types
b135a22... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
e0d2ffe... RISC-V: Add pattern for vector-scalar single widening float
284806c... RISC-V: Add pattern for vector-scalar dual widening floatin
49c1186... RISC-V: Add pattern for vector-scalar single widening float
81405ea... RISC-V: Add pattern for vector-scalar widening floating-poi
a23e0cd... RISC-V: Adjust tt-ascalon-d8 branch cost
9b07b82... RISC-V: Add pattern for vector-scalar single-width floating
030454f... RISC-V: Add pattern for vector-scalar single-width floating
ca083a4... RISC-V: Add pattern for vector-scalar single-width floating
eb1c109... RISC-V: Add pattern for vector-scalar widening floating-poi
264cbce... RISC-V: Add patterns for vector-scalar IEEE floating-point
ecc9920... gcc: introduce the dep_fusion pass
c2a5758... RISC-V: Add support for the XAndesvdot ISA extension.
e1dc28f... [RISC-V] Fix ordering of pipeline models
15c0132... RISC-V: Add support for the XAndesvpackfph ISA extension.
4ec4509... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
522fbd4... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
f41e005... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
be5a4e7... dep_fusion: Fix if target does not have macro fusion [PR121
753616e... gcc: introduce the dep_fusion pass
fe622bb... RISC-V: Add support for the XAndesvsintload ISA extension.
0116cf6... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
b35dca4... RISC-V: Add tt-ascalon-d8 pipeline description
fe7036a... [RISC-V] Adjust recently added test
49e97f1... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
b6f95a8... RISC-V: Allow errors to be suppressed when parsing architec
002fb3b... RISC-V: Adjust the vmacc.vx combine test cases
535a8d4... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
37565a1... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
b02e602... RISC-V: Fix extension subset check in riscv_can_inline_p
ff4fbd9... RISC-V: Add support for the XAndesbfhcvt ISA extension.
91df4d6... RISC-V: Add support for the XAndesperf ISA extension.
f7c5d8a... RISC-V: Add basic XAndes vendor extension support.
86f3add... RISC-V: Add pattern for vector-scalar floating-point max
2acdf01... [RISC-V][PR target/121213] Avoid unnecessary sign extension
6bf2209... RISC-V: Fix is_vlmax_len_p and use for strided ops.
8fa31a6... RISC-V: Add Zbb extension sext testcase.
54ba891... RISC-V: Update Zba 'shNadd.uw' testcase.`
9f4235f... RISC-V: Remove unused print_ext_doc_entry function [NFC]
a4d76a3... [RISC-V] Improve initial RTL generation for SImode adds on
ba3290f... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
68eb204... RISC-V: Add patterns for vector-scalar IEEE floating-point
21651cb... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
5117bea... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
3ce218d... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
db02e92... RISC-V: Add pattern for vector-scalar floating-point min
c8f7455... Remove xfail marker on RISC-V test
5dba2c9... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
184a0f0... More RISC-V testsuite hygiene
5ce1607... [committed] RISC-V Testsuite hygiene
03f89fc... [PATCH] RISC-V: Add pattern for reverse floating-point divi
136e651... [PATCH] RISC-V: Add pattern for vector-scalar single-width
8c35dda... Fix RISC-V bootstrap
31ddf2f... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
e2d6eb6... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
ba7b5c1... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
b6b08f6... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
575b89e... Fix invalid right shift count with recent ifcvt changes
a6bf8bf... [PR rtl-optimization/120553] Improve selecting between cons
46c6ad2... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
a19eae2... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
a7a6efe... [PR target/121213] Avoid unnecessary constant load in amosw
357b90b... regrename: treat writes as reads for fused instruction pair
c1129dc... ira: tie output allocnos for fused instruction pairs
6697f4c... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
e6d6f64... RISC-V: Update the comments of vx combine [NFC]
da9f5fe... RISC-V: Add missed DONE for vx combine pattern [NFC]
e8bb381... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
ee98f61... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
85e9eb2... [RISC-V][PR target/121531] Cover missing insn types in p400
f94e018... [RISC-V][PR target/121160] Avoid bogus force_reg call
ec46f42... [RISC-V][PR target/121113] Handle HFmode in various insn re
1447123... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
dbe8497... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
3e5fa7e... RISC-V: Expand const_vector with 2 elts per pattern.
14f89fa... Improve initial code generation for addsi/adddi
ca31f45... Don't run tests requiring "B" on designs without "B"
fbbe2dd... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
52be934... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
8062a51... RISC-V: Read extension data from riscv-ext*.def for arch-ca
16488bd... RISC-V: Support -march=unset
b1d4b7b... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
57d72fd... RISC-V: Add testcases for signed avg ceil vx combine
f4bd0c9... RISC-V: Adding H to the canonical order [PR121312]
1673475... RISC-V: Add testcases for unsigned avg ceil vx combine.
78442e9... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
62294f9... RISC-V: Remove use of structured binding to fix compiler wa
9d85b1e... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
9262657... RISC-V: Add test case for vaadd.vx combine polluting VXRM
d38a311... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
cf0277c... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
f9c27d4... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
c289ebe... RISC-V: Fix another vf FP16 combine run test failures
0d7ac2c... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
cf2129a... RISC-V: Prepare dynamic LMUL heuristic for SLP.
72543a1... RISC-V: Remove user-level interrupts
8f6f168... RISC-V: Add support for resumable non-maskable interrupt (R
c9eaaa6... riscv: testsuite: Fix misalignment check.
1a0cf11... RISC-V: Add test case for vx combine polluting VXRM
dd431ba... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
6a7bc07... RISC-V: Rework broadcast handling [PR121073].
239c4eb... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
003ac21... Change bellow in comments to below
dcb469c... [RISC-V] Restrict generic-vector-ooo DFA
5d48b1b... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
0088eef... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
c0e5a77... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
23e9bbb... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
da9aa51... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
9599d12... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
223df03... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
1be9436... RISC-V: Refine the test case for vector avg_floor and avg_c
52d14ed... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
be3d9c7... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
3ff05cc... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
02d96a4... RISC-V: Support RVVDImode for avg3_ceil auto vect
cf6c319... RISC-V: Fix vsetvl merge rule.
14c584d... RISC-V: Refine the scalar SAT_* test cases
7ed225c... RISC-V: Support RVVDImode for avg3_floor auto vect
c951d23... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
4077a4f... RISC-V: Add testcase for rv32 SAT_MUL from uint64
f92f580... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
37d07d1... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
60e9d7a... RISC-V: Make zero-stride load broadcast a tunable.
162fa5c... [RISC-V] Detect new fusions for RISC-V
5714040... RISCV: Remove the v extension requirement for sat scalar ru
61f7b6a... RISC-V: Add test for vec_duplicate + vssub.vv combine case
fe51701... RISC-V: Add test for vec_duplicate + vssub.vv combine case
a59c3a6... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
83f7bd9... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
eceb939... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
b2d6f7a... [RISC-V][PR target/120642] Avoid propagating constant AVL f
81f669b... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
c002455... RISC-V: Do not use vsetivli for THeadVector.
aa43dac... RISC-V: Ignore non-types in builtin function hash.
53d96ba... [committed][RISC-V] Fix testsuite fallout from check-functi
953f418... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
27d0274... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
3a1b3d4... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
5082e58... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
756881a... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
e2e337c... [RISC-V] Add basic instrumentation to fusion detection
724ea37... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
bec3307... Refactor record_function_versions.
ff7c2c9... [RISC-V][PR target/118886] Refine when two insns are signal
3426d7d... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
b1f931a... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
3dddca5... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
6b87b22... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
4149b5d... RISC-V: Reconcile the existing test due to cost model chang
400c15a... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
47bea53... RISC-V: Ignore -Oz for most rvv testcase [NFC]
c8933cb... RISC-V: Primary vector pipeline model for sifive 7 series
4383c1f... RISC-V: Adding B ext, fp16 and missing scalar instruction t
85f2082... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
32e1d40... RISC-V: Refactor the function bitmap_union_of_preds_with_en
24850c0... RISC-V: Add pipeline-checker script
0922b63... [RISC-V][PR target/119971] Avoid losing shift count masking
c234680... RISC-V: update prepare_ternary_operands to handle vector-sc
e37d44f... RISC-V: Fix build issue
1c07217... RISC-V: Add comment and reorder the the include files in ri
c73cb8a... RISC-V: Add Profiles RVA/B23S64 support.
ae9b218... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
0745a00... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
2fa0144... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
9a15d12... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
db8e41d... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
d8b9853... RISC-V: Fix ICE for expand_select_vldi [PR120652]
c0a02d4... [RISC-V] Force several tests to use rocket tuning
a389820... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
c40d74b... RISC-V: Add test for vec_duplicate + vminu.vv combine case
1ef09d0... RISC-V: Add test for vec_duplicate + vminu.vv combine case
75c16b9... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
25ea4cf... RISC-V: Add generic tune as default.
184b97d... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
f82585e... RISC-V: Adding cost model for zilsd
4db441a... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
0068288... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
c7ce525... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
56f7ca8... [PATCH v1] RISC-V: Use scratch reg for loop control
2fc718e... RISC-V: Add -fno-pie flags to testcases
720de21... RISC-V: Refine VX combine test case 0 to avoid code duplica
911d1b1... RISC-V: Update Profiles string in RV23.
e10112b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
1aed36e... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
f539a6f... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
11cbbb8... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
6e408d9... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
f369f19... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
3164d56... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
5830499... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
f0195f2... RISC-V: Prevent speculative vsetvl insn scheduling
97c34ce... RISC-V: Add patterns for vector-scalar negate-(multiply-add
9070724... RISC-V: testsuite: fix an obvious build error
c9bad40... RISC-V: Regen riscv-ext.texi [NFC]
3117ff8... RISC-V: Add test for vec_duplicate + vremu.vv combine case
b08b9e3... RISC-V: Add test for vec_duplicate + vremu.vv combine case
8b0489e... RISC-V: Reconcile the existing test for vremu.vx combine
b55e9a2... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
e3c45b9... [RISC-V] Enable more if-conversion on RISC-V
32faf90... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
81bebaf... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
c833dbc... RISC-V: Reconcile the existing test for vrem.vx combine
c93bc00... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
e0469f1... RISC-V: frm/mode-switch: robustify call_insn backtracking [
8939615... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
84ddf63... RISC-V: frm/mode-switch: remove dubious frm edge insertion
3442314... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
938afe9... [RISC-V] Handle 32bit operands in condition for conditional
9304697... [to-be-committed][RISC-V] Handle 32bit operands in conditio
503c73b... RISC-V: Reconcile the existing test for vdivu.vx combine
a768b6f... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
322e8b4... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
3e7db29... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
982fad6... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
60ee05d... [RISC-V] Improve signed division by 2^n
7dd5b77... RISC-V: Don't use structured binding in riscv-common.cc
7625380... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
b2889cf... [RISC-V] Improve sequences to generate -1, 1 in some cases.
7f2e263... RISC-V: Support Ssu64xl extension.
3020174... RISC-V: Support Sstvecd extension.
c15b3c1... RISC-V: Support Sstvala extension.
f028b49... RISC-V: Support Sscounterenw extension.
880e9dc... RISC-V: Support Ssccptr extension.
de642fe... RISC-V: Support Smrnmi extension.
01fea86... RISC-V: Support Sm/scsrind extensions.
d9a1933... RISC-V: Update extension defination.
2e83517... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
628e3ac... [PATCH v2] RISC-V: Add svbare extension.
a36e2ca... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
258a7a9... RISC-V: Add Shlcofideleg extension.
6c233df... RISC-V: Reconcile the existing test for vdiv.vx combine
8d14b6c... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
98f1332... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
a142182... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
aee9cdd... RISC-V: Use helper function to get FPR to VR move cost
cf38773... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
ded810d... [PATCH] RISC-V: Add smcntrpmf extension.
7244f8f... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
be260da... RISC-V: Implement full-featured iterator for riscv_subset_l
a8ec06c... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
b4f3d0e... RISC-V: Fix line too long format issue for autovect.md [NFC
bc19900... RISC-V: Add test cases for avg_ceil vaadd implementation
1bb6166... RISC-V: Reconcile the existing test for avg_ceil
dba586a... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
26f85a8... RISC-V: Add minimal support of double trap extension 1.0
5be4801... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
d384abf... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
f7cabe8... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
08a76e6... RISC-V: Avoid division by zero in check_builtin_call [PR120
1fdbc4c... RISC-V: Add test cases for avg_floor vaadd implementation
257289e... RISC-V: Reconcile the existing test for avg_floor
70e894e... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
f097cdb... [RISC-V] Add andi+bclr synthesis
e9ff3ab... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
dec63a8... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
8a8dc0b... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
01d86ed... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
d6e01fa... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
edc2eca... [RISC-V] shift+and+shift for logical and synthesis
88efeee... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
eefcfe5... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
7b1c295... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
7288754... RISC-V: Support CPUs in -march.
dcc501f... RISC-V: Add autovec mode param.
43162a4... RISC-V: Default-initialize variable.
20b4617... RISC-V: Fix some dynamic LMUL costing.
12a0ffa... [RISC-V] Clear both upper and lower bits using 3 shifts
c9f2fca... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
1977f8b... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
87d05fe... [RISC-V] Clear high or low bits using shift pairs
a5445e4... [RISC-V] Improve (x << C1) + C2 split code
787e396... [RISC-V][PR target/120368] Fix 32bit shift on rv64
587fcc2... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
93c36d2... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
5e47970... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
701ba62... [RISC-V] Infrastructure of synthesizing logical AND with co
b0bcb4e... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
9d42146... [PATCH v2 1/2] The following changes enable P8700 processor
327a4cf... [RISC-V] Avoid multiple assignments to output object
38f7ba9... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
f954c16... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
87fb9af... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0e1cfc7... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
ed70e05... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
a9a1017... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
72a13e0... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
311c474... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
f907040... [committed][RISC-V][PR target/120333] Remove bogus bext pat
3fb8293... [RISC-V] Fix false positive from Wuninitialized
a130d20... RISC-V: Fix the warning of temporary object dangling refere
8381ff3... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
5e3190e... RISC-V: Support Zilsd code gen
e27f8f8... RISC-V: Add new operand constraint: cR
9d9740a... [RISC-V] Fix ICE due to bogus use of gen_rtvec
e9be6f2... [RISC-V] Avoid setting output object more than once in IOR/
c4a8a1f... RISC-V: Since the loop increment i++ is unreachable, the lo
56d4d5c... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
aa98292... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
054b1d0... Make end_sequence return the insn sequence
ba3ec40... RISC-V: Reuse test name for vx combine test data [NFC]
d017da4... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
4aab909... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
26057c0... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
5d2571a... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
c2873e8... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
da2c054... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
e13a035... RISC-V: Adjust vx combine test case to avoid name conflict
f497f30... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
23ae176... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
d9d2650... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
5fbbe8e... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
3723b04... RISC-V: Add augmented hypervisor series extensions.
2054408... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
fbac98a... RISC-V: Regen riscv-ext.opt.urls
c6c59ba... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
4c85846... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
84d1d70... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
a5141fc... RISC-V: Introduce riscv_ext_info_t to hold extension metada
ae18da5... RISC-V: Adjust riscv_can_inline_p
d656879... RISC-V: Generate extension table in documentation from risc
af7d498... RISC-V: Use riscv-ext.def to generate target options and va
a2495b8... RISC-V: Introduce riscv-ext*.def to define extensions
4b8425a... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
317b87a... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
324b7ce... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
96b6084... RISC-V: Support for zilsd and zclsd extensions.
cfb4064... testsuite: Fix RISC-V arch-52.c format issue.
ee21d98... RISC-V: Support RISC-V Profiles 23.
1fc5c6e... RISC-V: Support RISC-V Profiles 20/22.
963905f... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
db6cefb... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
d653b0d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
4254554... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
8f0927d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
f9cb05e... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
5ac60df... RISC-V: Separate the test running of rvv vx_vf
8bff3e3... [RISC-V][PR target/120137][PR target/120154] Don't create o
0ee3378... [PATCH] RISC-V: Minimal support for zama16b extension.
4d120bb... [RISC-V] Avoid unnecessary andi with -1 argument
a71e279... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
742ce46... [PATCH] RISC-V: Recognized svadu and svade extension
faf7f8b... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
aa7ff63... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
a9df266... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
7855267... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
be40a5a... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
3b95719... RISC-V: Add gr2vr cost helper function
78976e4... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
f420f1e... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
c932d73... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
8d39353... [V2][RISC-V] Trivial permutation constant derivation
2cf6ccf... [RISC-V] Adjust rvv tests after recent jump threading chang
1f43143... [PATCH] RISC-V: Implment H modifier for printing the next r
bf2957e... [to-be-committed][RISC-V] Adjust testcases and finish regis
a3e05b6... RISC-V: Remove unnecessary frm restore volatile define_insn
1c071ee... RISC-V: Allow different dynamic floating point mode to be m
b17b29f... RISC-V: Fix missing implied Zicsr from Zve32x
267b826... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
2b1a22e... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
6627ec0... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
4519ab1... RISC-V: Extract vector stepped for expand_const_vector [NFC
98b4405... RISC-V: Extract vector duplicate for expand_const_vector [N
e33c2ec... RISC-V: Extract vec_series for expand_const_vector [NFC]
7bb01d0... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
eca9631... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
3428a2b... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
3a1daa0... [riscv] vec_dup immediate constants in pred_broadcast expan
208c0d6... [RISC-V][PR target/119865] Don't free ggc allocated memory
52c6cb8... [RISC-V][PR target/118410] Improve code generation for some
3d9fe66... [RISC-V] Fix missed bext discovery
a0e1b6f... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
d6a0e77... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
233fc87... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
8a04a2d... RISC-V: Fix indexed store output template [PR123780].
cabf339... RISC-V: Add zvfbfmin to tt-ascalon-d8's extension list [PR1
0f45a78... forwprop: More nop-conversion handling [PR123731].
a73d879... RISC-V: Correct builtin registration order [PR123279].
74b6f76... [PR rtl-optimization/123380] Avoid creating bogus SUBREG in
9395545... [RISC-V][PR target/123626] Fix VXRM state after calls
f5b3444... [RISC-V][PR rtl-optimization/121787] Work around bad cfglay
d960392... [PR target/113666] Simplify VEC_EXTRACT from a uniform vect
4253fad... doc, riscv: Clean up documentation of RISC-V options [PR122
c7e2c2e... vect: Make SELECT_VL a convert optab.
e95a3a9... forwprop: Allow nop conversions for vector constructor.
44385e8... forwprop: allow subvectors in simplify_vector_constructor (
2f7f6ea... forwprop: Check type conversion in pack/unpack [PR123117].
321af35... [PR target/121778] Improving rotation detection
741eadb... Fix RISC-V test after recent vectorizer changes
5ce0e74... RISC-V: Enable the ZD constraint only when xmipscbop is ena
40708ea... match: Add simplification of `(a*zero_one_valued_p) & b` if
e95868c... ifcvt: Improve `cmp?a&b:a` to try with -1 [PR123312]
1eca8c1... forwprop: Fix type mismatch in vec constructor [PR123525].
4eb6fe9... if-conv: Prevent vector types in scalar cond reduction [PR1
f900036... rtlanal: Determine nonzero bits of popcount from operand [P
a04729d... VN: Fix VN ICE for large _BitInt types
cb8b842... RISC-V: Add support for _BitInt [PR117581]
58ef612... forwprop: Use ssizetype for mask [PR123414].
410479d... RISC-V: Update tt-ascalon-d8's extension list [PR123492]
aa00cf2... ifcvt: Reject inner floating modes of a subreg for noce_try
b47b7a3... [RISC-V] Clamp long reservations to 7c
bc3efb7... [PATCH v3] match.pd: popcount(X & -X) -> -X != 0 [PR102486]
e4f9b0a... [RISC-V] Restore inline expansion of block moves on RISC-V
147bd97... [PATCH v1 2/2] RISC-V: Add run test case for vwadd/vwsub wx
272f5cb... [PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for an
573330b... RISC-V: Adjust the asm check of vx_vf due to middle-end cha
c052bb0... Vect: Adjust depth_limit of vec_slp_has_scalar_use from 2 t
a9eb442... Partially revert patch that made VXRM a global register on
1cb3326... [PR target/123010] Simplify shift of sign extracted field t
addb12a... [RISC-V][PR target/121485] Fix mode on Zvkned lmul extendin
c4bc883... [RISC-V][PR target/123318] Use a Pmode temporary for output
f734eff... ifcvt: Allow non-comparisons against 0 in noce_try_cond_zer
89ed849... ifcvt: Handle lowpart subregs if noce_emit_cmove fails in n
2b85b99... ifcvt: cleanup if_info->cond usage in noce_try_cond_zero_ar
28341aa... simplify-rtx: Fix up (ne (ior (ne x 0) y) 0) simplification
82849bb... Revert "ifcvt: Move noce_try_cond_zero_arith last"
0c13c7a... [RISC-V][PR target/123283] Wrap naked REG operands with a U
8591a7e... doc: make regenerate-opt-urls
ee0e110... doc, riscv: Clean up RISC-V extensions documentation
51f25b2... RISC-V: Add test for vec_duplicate + vmsleu.vv combine with
9b63f51... RISC-V: Combine vec_duplicate + vmsleu.vv to vmsleu.vx on G
29f271f... ifcvt: Move noce_try_cond_zero_arith last
2a3d3bd... ifcvt: Only allow scalar integral modes for noce_try_cond_z
029804e... [committed][RISC-V][PR target/123274] Add missing condition
3e7b3b0... [RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 s
e479abf... [RISC-V][PATCH] Adjust clmul latency in Spacemit X60 schedu
f178c60... ifcvt: Fix noce_try_cond_zero_arith after get_base_reg chan
d460202... [RISC-V][V2] Improve spill code for RVV slightly to fix reg
ca47b96... ifcvt: cond zero arith: handle subreg for shift count
82a1ec9... ifcvt: cond zero arith: elide short forward branch for sign
5617ebc... ifcvt: cond zero arith: re-expand output pattern [NFC]
e8c050f... ifcvt: cond zero arith: factor out common noce_emit_czero e
bb13f8d... ifcvt: cond zero arith: opencode helper noce_bbs_ok_for_con
6a436dd... [RISC-V][V2] Improve spill code for RVV slightly to fix reg
49cb2c3... RISC-V: Fix overflow check in interleave pattern [PR122970]
2667884... RISC-V: Testsuite fixes.
766cd9d... RISC-V: Generic vec_extract via subreg.
6f2c787... RISC-V: Add VLS modes to autovec iterators.
dbc5e5f... RISC-V: Rename vector-mode related functions.
f7ab658... RISC-V: Change gather/scatter iterators.
139e878... Fix various RISC-V testsuite regressions after volatile pat
f3f18bc... [PATCH] RISC-V: Rename UPPERCAE_NAME to UPPERCASE_NAME
74d2685... RISC-V: Add test for vec_duplicate + vmslt.vv combine with
1e5e925... RISC-V: Combine vec_duplicate + vmslt.vv to vmslt.vx on GR2
a4dd08e... RISC-V: Regenerate opt urls.
babd144... RISC-V: -mmax-vectorization.
cf695e3... vect: Add vect-scalar-cost-multiplier for SLP.
7e7f390... middle-end: Add new parameter to scale scalar loop costing
1eac1cd... RISC-V: Pragma target [PR115325].
5636286... RISC-V: Implement mask reduction.
60fe999... [riscv] avoid auipc overflow with large offsets [PR91420]
0fd5724... RISC-V: Add test for vec_duplicate + vmsltu.vv combine with
2ca500e... RISC-V: Combine vec_duplicate + vmsltu.vv to vmsltu.vx on G
7874246... RISC-V: Remove unused placeholder_p parameter from add_func
183cac7... [PATCH][PR target/122942] RISC-V: Add zifencei extension to
b2f5cde... riscv: RISCV backend, meet C++20
a3f0414... RISC-V: Emit \n\t at the end of instruction instead of ;
0b563fa... RISC-V: Support --with-cpu
f48fdf5... RISC-V: Add SpacemiT extension xsmtvdot
19e354a... RISC-V: Run gen-riscv-ext-opt to regenerate riscv-ext.opt [
0c52681... RISC-V: Add Andes 45 series pipeline description.
d23fbca... RISC-V: Add Andes 23 series pipeline description.
c635fb6... RISC-V: Fix one typo result in pr121959-run-1 run failure
e4aa812... Revert "[PATCH v3] RISC-V: Implement RISC-V profile macro s
f07194a... RISC-V: Add testcase for unsigned scalar SAT_MUL form 7
48b66cf... RISC-V: Add BF VLS modes and document iterators.
60d1108... [PR rtl-optimization/122782] Fix out of range shift causing
e219ef0... [PR 122701] Emit fresh reg->reg copy rather than modifying
1eb25be... [PR118358, LRA]: Decrease pressure after issuing input relo
bed713f... RISC-V: Add RTL pass to combine cm.popret with zero return
cc694fa... [RISC-V] Fix trivial bootstrap failure on RISC-V
f832f98... RISC-V: Add flag to adjust mem inlining threshold
a0774fb... [RISC-V] Add cpu and tuning structures for spacemit-x60 des
21124cc... RISC-V: Remove gather scale and offset handling.
0685728... [PR rtl-optimization/122575] Fix mode on optimized IOR comp
b6f7225... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
e926f50... RISC-V: Add test for vec_duplicate + vmsne.vv combine case
b5fa025... [RISC-V] Avoid most calls to gen_extend_insn
5940c73... [RISC-V] Drop scan-tests of marginal value
fdb1409... RISC-V: Add missing member for andes_25_tune_info
ea50736... Handle shift-pairs in ext-dce for targets without zero/sign
1c627f2... RISC-V: Add Andes 25 series pipeline description.
ab2bd5e... [RISC-V] Improve detection of packw
e8935a0... [RISC-V] Simplify riscv_extend_to_xmode_reg
0f625ab... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
2532965... RISC-V: Add test for vec_duplicate + vmseq.vv combine case
6bc83fc... [RISC-V] Add testcase for shifted truthvalue
34ed227... RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB
4409fac... RISC-V: Add test for vec_duplicate + vwmaccu.vv combine wit
956d0b8... RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmac
7593a1c... [RISC-V] Ignore useless zero-initialization in conditional
0647bbb... [RISC-V][PR 121136] Improve various tests which only need t
2c08dd7... RISC-V: testsuite: Fix pr119115.c.
e2215da... [PR rtl-optimization/122536] Fix guard against variable bit
8b585ef... RISC-V: Fix the ABI of empty unions and zero length array i
6564264... [RISC-V][PR tree-optimization/52345] Optimize testing multi
fed48cd... [RISC-V] Expose sign extension for 32 bit rotates by consta
89ad219... gcc: Drop junk vim backup file
2246e8a... [RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR
b7d331b... [RISC-V] Reorder ready queue slightly to avoid unnecessary
e7133b9... tree-optimization/122502 - avoid folding during imm use wal
31431ca... niter: Use ranger to query ctz range.
f361263... [PATCH v2] RISC-V: avlprop: Scale AVL by subreg ratio [PR12
3c2b0c1... RISC-V: Clean up build warnings for VLS calling convention
5febf43... Skip riscv/rvv/xtheadvector/pr116593.C if not hostedlib
85f0c9b... RISC-V: Add testsuite for fixed-length vector calling conve
f97f173... RISC-V: Add testsuite for fixed-length vector calling conve
4df1d6d... RISC-V: Implement standard fixed-length vector calling conv
1de45ed... [RISC-V][PR target/64345][PR tree-optimization/80770] Impro
6aab296... Increase NUM_ABI_IDS to support RISC-V VLS calling conventi
e6ada5e... [PATCH v2] RISC-V: Fix moving data from V_REGS to GR_REGS b
cfd196a... Fix minor RISC-V testsuite failure
752a049... Fix minor testsuite scan failures for RISC-V
5cb1e03... RISC-V: Add testcase for unsigned scalar SAT_MUL form 6
fa03db1... RISC-V: Fix incorrect op of vwaddu/vwsubu wx combine
99611ce... [PATCH v3] RISC-V: Implement RISC-V profile macro support
0b62abf... [RISC-V][PR target/120811] Improving address reloads in LRA
e475209... [PR target/119587] RISC-V: xtheadmemidx: Split slli.uw patt
9e7cdc1... [RISC-V] Improve subword atomic patterns in sync.md
431f76f... RISC-V: Add test for vec_duplicate + vwsubu.wv combine with
7c907a9... RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on G
0d700e5... RISC-V: Allow VLS types using up to LMUL 8
d3cb920... [PATCH] RISC-V: Fix slide pattern recognition [PR122124]
416aa8e... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
771da3a... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
418ce50... Fixup merge conflict
104fdc6... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
d2fd42f... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
20f7c4b... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
09e6759... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
562c0e2... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
4c51850... [RISC-V][PR target/122106] Add missing predicate on crc exp
0854487... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
e0c6fef... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
a51a5b6... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
e00d13e... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
7690605... RISC-V: Improve slide patterns recognition
d9edc1f... RISC-V: Only Save/Restore required registers for ILP32E/LP6
2f4f123... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
bc8043d... RISC-V: Correct lmul estimation
db3beb9... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
4367b40... [PR tree-optimization/58727] Don't over-simplify constants`
868de7f... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
4744def... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
84dd51f... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
c27fff1... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
c23e682... RISC-V: Allow profiles input in '--with-arch' option.
e62a2bb... RISC-V: Configure Profiles definitions in the definition fi
fdbebd8... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
05761f0... Widening-Mul: Refine build_and_insert_cast when rhs is cast
fa9bfb3... RISC-V: Fix vendor intrinsic tests for disabled multilib co
5e1d885... RISC-V: Support vnclip idiom testcase [PR120378]
3aab45a... Match: Support SAT_TRUNC variant NARROW_CLIP
fe3a4fc... [RISC-V] Adjust ABI specification in recently added Andes t
f4a6887... RISC-V: Suppress cross CC sibcall optimization from vector
e2b86ab... RISC-V: Add min/max patterns for ifcvt.
e443719... ifcvt: Clarify if_info.original_cost.
5266384... RISC-V: Fix can_find_related_mode_p for VLS types
a944484... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
94be3df... RISC-V: Add pattern for vector-scalar single widening float
531e390... RISC-V: Add pattern for vector-scalar dual widening floatin
dc9fafa... RISC-V: Add pattern for vector-scalar single widening float
26da44c... RISC-V: Add pattern for vector-scalar widening floating-poi
f62f5ae... RISC-V: Adjust tt-ascalon-d8 branch cost
7307f41... RISC-V: Add pattern for vector-scalar single-width floating
249a102... RISC-V: Add pattern for vector-scalar single-width floating
d4f4179... RISC-V: Add pattern for vector-scalar single-width floating
8398e11... RISC-V: Add pattern for vector-scalar widening floating-poi
9814978... RISC-V: Add patterns for vector-scalar IEEE floating-point
2eef393... gcc: introduce the dep_fusion pass
6011a0d... RISC-V: Add support for the XAndesvdot ISA extension.
2aeb0ef... [RISC-V] Fix ordering of pipeline models
6fa3146... RISC-V: Add support for the XAndesvpackfph ISA extension.
043a34a... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
b7e9b63... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
a3d7613... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
4a9beaf... dep_fusion: Fix if target does not have macro fusion [PR121
dde0ae9... gcc: introduce the dep_fusion pass
88aac2d... RISC-V: Add support for the XAndesvsintload ISA extension.
d3bf8c5... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
f1915f8... RISC-V: Add tt-ascalon-d8 pipeline description
831a900... [RISC-V] Adjust recently added test
29c4a5b... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
a24f611... RISC-V: Allow errors to be suppressed when parsing architec
e160377... RISC-V: Adjust the vmacc.vx combine test cases
c36c378... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
908dfa9... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
fcc6e88... RISC-V: Fix extension subset check in riscv_can_inline_p
c3bf606... RISC-V: Add support for the XAndesbfhcvt ISA extension.
3854452... RISC-V: Add support for the XAndesperf ISA extension.
60886f9... RISC-V: Add basic XAndes vendor extension support.
da3370c... RISC-V: Add pattern for vector-scalar floating-point max
189487b... [RISC-V][PR target/121213] Avoid unnecessary sign extension
fbf6932... RISC-V: Fix is_vlmax_len_p and use for strided ops.
5fc0dea... RISC-V: Add Zbb extension sext testcase.
0a98892... RISC-V: Update Zba 'shNadd.uw' testcase.`
959d524... RISC-V: Remove unused print_ext_doc_entry function [NFC]
7fca6d0... [RISC-V] Improve initial RTL generation for SImode adds on
8973dd9... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
67b8f43... RISC-V: Add patterns for vector-scalar IEEE floating-point
153fd80... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
81d03d7... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
de4b993... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
58b4a43... RISC-V: Add pattern for vector-scalar floating-point min
57079d8... Remove xfail marker on RISC-V test
23692a8... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
c76c769... More RISC-V testsuite hygiene
cdebbe3... [committed] RISC-V Testsuite hygiene
68564d0... [PATCH] RISC-V: Add pattern for reverse floating-point divi
f7a7aac... [PATCH] RISC-V: Add pattern for vector-scalar single-width
3f3c12b... Fix RISC-V bootstrap
de5bda9... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
81cb839... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
f11500b... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
772f499... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
b10f2cd... Fix invalid right shift count with recent ifcvt changes
2b85093... [PR rtl-optimization/120553] Improve selecting between cons
9a6d002... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
579e083... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
ad1addb... [PR target/121213] Avoid unnecessary constant load in amosw
6b61011... regrename: treat writes as reads for fused instruction pair
1f84325... ira: tie output allocnos for fused instruction pairs
fcfaa03... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
42b9e54... RISC-V: Update the comments of vx combine [NFC]
1bd712d... RISC-V: Add missed DONE for vx combine pattern [NFC]
6b0d7b9... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
18c09a8... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
9a677c9... [RISC-V][PR target/121531] Cover missing insn types in p400
9cadee1... [RISC-V][PR target/121160] Avoid bogus force_reg call
964c2e5... [RISC-V][PR target/121113] Handle HFmode in various insn re
6bf7e80... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
dfeeb93... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
530ee19... RISC-V: Expand const_vector with 2 elts per pattern.
f7a013b... Improve initial code generation for addsi/adddi
96e45b3... Don't run tests requiring "B" on designs without "B"
4bbb209... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
8cdd651... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
05b45a5... RISC-V: Read extension data from riscv-ext*.def for arch-ca
67ff0fd... RISC-V: Support -march=unset
e07f32b... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
7caaa6b... RISC-V: Add testcases for signed avg ceil vx combine
7eaccc4... RISC-V: Adding H to the canonical order [PR121312]
fb31281... RISC-V: Add testcases for unsigned avg ceil vx combine.
c133ecf... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
a2eab7f... RISC-V: Remove use of structured binding to fix compiler wa
5f9a794... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
813cf47... RISC-V: Add test case for vaadd.vx combine polluting VXRM
cf1e742... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
31c1842... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
965a8ff... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
90d6531... RISC-V: Fix another vf FP16 combine run test failures
290b844... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
cebff5b... RISC-V: Prepare dynamic LMUL heuristic for SLP.
3efdbe8... RISC-V: Remove user-level interrupts
264e75c... RISC-V: Add support for resumable non-maskable interrupt (R
ecdd070... riscv: testsuite: Fix misalignment check.
7e88f73... RISC-V: Add test case for vx combine polluting VXRM
cea9722... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
b9e4adb... RISC-V: Rework broadcast handling [PR121073].
f09fafd... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
3d98896... Change bellow in comments to below
7b7870e... [RISC-V] Restrict generic-vector-ooo DFA
6240b43... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
2060bb2... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
739bce9... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
1af177c... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
f0d0646... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
4b951cf... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
4412389... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
e05e5b7... RISC-V: Refine the test case for vector avg_floor and avg_c
f908584... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
1a43607... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
52c5a4a... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
97e7f86... RISC-V: Support RVVDImode for avg3_ceil auto vect
d57c5a1... RISC-V: Fix vsetvl merge rule.
0344537... RISC-V: Refine the scalar SAT_* test cases
63b29f8... RISC-V: Support RVVDImode for avg3_floor auto vect
f7400ae... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
501314b... RISC-V: Add testcase for rv32 SAT_MUL from uint64
6627357... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
ea0f73f... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
6b643b7... RISC-V: Make zero-stride load broadcast a tunable.
de85926... [RISC-V] Detect new fusions for RISC-V
9b85f8f... RISCV: Remove the v extension requirement for sat scalar ru
8b6a300... RISC-V: Add test for vec_duplicate + vssub.vv combine case
f0a22a5... RISC-V: Add test for vec_duplicate + vssub.vv combine case
c926032... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
b9e5cf1... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
bd45518... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
9463123... [RISC-V][PR target/120642] Avoid propagating constant AVL f
42e6ad9... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
ada1d23... RISC-V: Do not use vsetivli for THeadVector.
02996b0... RISC-V: Ignore non-types in builtin function hash.
465d0cc... [committed][RISC-V] Fix testsuite fallout from check-functi
1e3f113... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
781200d... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
67231bb... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
6bf0784... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
0dbc2ba... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
70f923d... [RISC-V] Add basic instrumentation to fusion detection
ffb3779... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
6d9dc5f... Refactor record_function_versions.
961f74c... [RISC-V][PR target/118886] Refine when two insns are signal
6d58c0a... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
e2ba7f3... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
8b61131... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
bd1529a... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
308490a... RISC-V: Reconcile the existing test due to cost model chang
0ab6d94... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
7bcda0b... RISC-V: Ignore -Oz for most rvv testcase [NFC]
e3e0941... RISC-V: Primary vector pipeline model for sifive 7 series
6d2e28c... RISC-V: Adding B ext, fp16 and missing scalar instruction t
216d94c... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
727a27a... RISC-V: Refactor the function bitmap_union_of_preds_with_en
57a5ef2... RISC-V: Add pipeline-checker script
0a60315... [RISC-V][PR target/119971] Avoid losing shift count masking
9dcfbb0... RISC-V: update prepare_ternary_operands to handle vector-sc
f7c0c42... RISC-V: Fix build issue
7e25f4d... RISC-V: Add comment and reorder the the include files in ri
7139270... RISC-V: Add Profiles RVA/B23S64 support.
1141c0d... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
8af8876... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
523d251... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
24079fd... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
4364800... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
eb2aa8e... RISC-V: Fix ICE for expand_select_vldi [PR120652]
1b09180... [RISC-V] Force several tests to use rocket tuning
5274287... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
9041b60... RISC-V: Add test for vec_duplicate + vminu.vv combine case
44b9ee7... RISC-V: Add test for vec_duplicate + vminu.vv combine case
b42e047... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
820014b... RISC-V: Add generic tune as default.
de52ced... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
f70b90b... RISC-V: Adding cost model for zilsd
abbfffc... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
244a6ea... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
35b7fc1... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
dbbc1bd... [PATCH v1] RISC-V: Use scratch reg for loop control
50efec3... RISC-V: Add -fno-pie flags to testcases
7898db6... RISC-V: Refine VX combine test case 0 to avoid code duplica
2181767... RISC-V: Update Profiles string in RV23.
9f910ac... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
8f026fd... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
29d6c62... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
d246a27... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
07547f4... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
a534eb4... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
74655b1... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
51579a8... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
0f499c6... RISC-V: Prevent speculative vsetvl insn scheduling
e5f1234... RISC-V: Add patterns for vector-scalar negate-(multiply-add
6cbaecb... RISC-V: testsuite: fix an obvious build error
db21d26... RISC-V: Regen riscv-ext.texi [NFC]
a863d12... RISC-V: Add test for vec_duplicate + vremu.vv combine case
9526ecf... RISC-V: Add test for vec_duplicate + vremu.vv combine case
1d230e1... RISC-V: Reconcile the existing test for vremu.vx combine
3a96680... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
cf9e61e... [RISC-V] Enable more if-conversion on RISC-V
b103d80... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
1bcf5c1... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
b1f7bbf... RISC-V: Reconcile the existing test for vrem.vx combine
ca6cc88... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
798ac71... RISC-V: frm/mode-switch: robustify call_insn backtracking [
5bdb166... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
ed2f2bd... RISC-V: frm/mode-switch: remove dubious frm edge insertion
30b3297... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
42e8965... [RISC-V] Handle 32bit operands in condition for conditional
2b04d1b... [to-be-committed][RISC-V] Handle 32bit operands in conditio
5eaf372... RISC-V: Reconcile the existing test for vdivu.vx combine
2d990c7... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
29f5076... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
b42ecfd... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
7674590... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
3ee4f6c... [RISC-V] Improve signed division by 2^n
3877584... RISC-V: Don't use structured binding in riscv-common.cc
cf27023... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
b34293e... [RISC-V] Improve sequences to generate -1, 1 in some cases.
33fc3a8... RISC-V: Support Ssu64xl extension.
c39c56f... RISC-V: Support Sstvecd extension.
792e189... RISC-V: Support Sstvala extension.
90975f3... RISC-V: Support Sscounterenw extension.
b4033da... RISC-V: Support Ssccptr extension.
b86f856... RISC-V: Support Smrnmi extension.
f5ee044... RISC-V: Support Sm/scsrind extensions.
2a11c43... RISC-V: Update extension defination.
6ba12bb... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
dd201e9... [PATCH v2] RISC-V: Add svbare extension.
3dbc97c... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
07c4389... RISC-V: Add Shlcofideleg extension.
ffb3cf1... RISC-V: Reconcile the existing test for vdiv.vx combine
a7e262c... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
03a9b55... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
e9061d2... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
5923991... RISC-V: Use helper function to get FPR to VR move cost
624bd8b... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
b6d4223... [PATCH] RISC-V: Add smcntrpmf extension.
83588f4... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
55099db... RISC-V: Implement full-featured iterator for riscv_subset_l
334603a... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
4343ff5... RISC-V: Fix line too long format issue for autovect.md [NFC
baa04ca... RISC-V: Add test cases for avg_ceil vaadd implementation
ecdaaa5... RISC-V: Reconcile the existing test for avg_ceil
5e4d741... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
697db4d... RISC-V: Add minimal support of double trap extension 1.0
0b5f163... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
3626c3d... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
d7041e9... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
0a851f9... RISC-V: Avoid division by zero in check_builtin_call [PR120
f575521... RISC-V: Add test cases for avg_floor vaadd implementation
0d8cfd9... RISC-V: Reconcile the existing test for avg_floor
b485175... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
b26ed27... [RISC-V] Add andi+bclr synthesis
2809986... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
41e33c2... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
58ac528... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
e697e12... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
f08bb07... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
9166c80... [RISC-V] shift+and+shift for logical and synthesis
dbc15a6... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
675156c... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
3db9a27... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
8df611a... RISC-V: Support CPUs in -march.
0f42549... RISC-V: Add autovec mode param.
d10b336... RISC-V: Default-initialize variable.
590060a... RISC-V: Fix some dynamic LMUL costing.
d0ec022... [RISC-V] Clear both upper and lower bits using 3 shifts
71340d7... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
eb3b16f... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
06d3969... [RISC-V] Clear high or low bits using shift pairs
672b95e... [RISC-V] Improve (x << C1) + C2 split code
027668a... [RISC-V][PR target/120368] Fix 32bit shift on rv64
149327c... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
8398aa0... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
e8ce01a... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
92c38c0... [RISC-V] Infrastructure of synthesizing logical AND with co
f67fb0a... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
5cb1975... [PATCH v2 1/2] The following changes enable P8700 processor
293fabe... [RISC-V] Avoid multiple assignments to output object
c8696d5... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
03a48c1... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0d7c926... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
859a8bd... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
365cb98... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
ba7716b... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
4dff34d... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
55ed1c7... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
e0ba1b7... [committed][RISC-V][PR target/120333] Remove bogus bext pat
e04ba84... [RISC-V] Fix false positive from Wuninitialized
c5c416e... RISC-V: Fix the warning of temporary object dangling refere
e8e69ad... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
eb1bb4f... RISC-V: Support Zilsd code gen
513d446... RISC-V: Add new operand constraint: cR
a21e0ef... [RISC-V] Fix ICE due to bogus use of gen_rtvec
29d2101... [RISC-V] Avoid setting output object more than once in IOR/
e58d844... RISC-V: Since the loop increment i++ is unreachable, the lo
2c33ea9... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
b5a68a6... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
beaece8... Make end_sequence return the insn sequence
f2e87b8... RISC-V: Reuse test name for vx combine test data [NFC]
4ad1a78... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
de291ec... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
bd79642... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
f14a2d3... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
8da084b... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
6c53afd... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
4ae8aa7... RISC-V: Adjust vx combine test case to avoid name conflict
f57b8c5... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
76b7ce7... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
38d9543... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
475abd8... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
afb71b6... RISC-V: Add augmented hypervisor series extensions.
dad42f9... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
7845c46... RISC-V: Regen riscv-ext.opt.urls
b2bd266... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
0cfd473... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
432dd9f... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
72c30ab... RISC-V: Introduce riscv_ext_info_t to hold extension metada
18ca785... RISC-V: Adjust riscv_can_inline_p
65dd635... RISC-V: Generate extension table in documentation from risc
e17a060... RISC-V: Use riscv-ext.def to generate target options and va
929b57d... RISC-V: Introduce riscv-ext*.def to define extensions
801c8bd... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
7ebf555... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
8f46ee1... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
3e55f1a... RISC-V: Support for zilsd and zclsd extensions.
5fc465c... testsuite: Fix RISC-V arch-52.c format issue.
e60608f... RISC-V: Support RISC-V Profiles 23.
27f3e91... RISC-V: Support RISC-V Profiles 20/22.
a4770ea... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
d3d787b... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
77de0b9... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
968a444... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
b553186... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
bbfb3eb... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
0be0cd3... RISC-V: Separate the test running of rvv vx_vf
1b5ee7f... [RISC-V][PR target/120137][PR target/120154] Don't create o
f898cbc... [PATCH] RISC-V: Minimal support for zama16b extension.
1b1c88e... [RISC-V] Avoid unnecessary andi with -1 argument
528c985... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
e8ed556... [PATCH] RISC-V: Recognized svadu and svade extension
8fec619... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
98bfdd1... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
79baf85... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
5a6fd7d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
0ca2857... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
45da849... RISC-V: Add gr2vr cost helper function
9847056... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
f765334... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
9f8e857... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
977051a... [V2][RISC-V] Trivial permutation constant derivation
ccc0703... [RISC-V] Adjust rvv tests after recent jump threading chang
43aef40... [PATCH] RISC-V: Implment H modifier for printing the next r
ebfad14... [to-be-committed][RISC-V] Adjust testcases and finish regis
513e213... RISC-V: Remove unnecessary frm restore volatile define_insn
fb89745... RISC-V: Allow different dynamic floating point mode to be m
53267e8... RISC-V: Fix missing implied Zicsr from Zve32x
46274ec... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
8e67ba9... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
64f1f4e... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
adc2765... RISC-V: Extract vector stepped for expand_const_vector [NFC
59aaf50... RISC-V: Extract vector duplicate for expand_const_vector [N
f467831... RISC-V: Extract vec_series for expand_const_vector [NFC]
469f9d7... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
358489b... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
c5bb7ca... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
a86b400... [riscv] vec_dup immediate constants in pred_broadcast expan
ebf278e... [RISC-V][PR target/119865] Don't free ggc allocated memory
a3ddbff... [RISC-V][PR target/118410] Improve code generation for some
1e42f94... [RISC-V] Fix missed bext discovery
c39ee1a... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
1fa458c... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
6ecfe86... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
c0aae47... LoongArch: Remove unused function type. (*)
3534d9a... LoongArch: Fix bug123766. (*)
7d89070... LoongArch: Fix bug123807. (*)
637afdf... Daily bump. (*)
ed185d8... Ada: Fix internal error on equality test with empty contain (*)
3b48469... d: Fix Segmentation fault with redeclared symbols [PR123407 (*)
ed65c1d... d: Fix ICE in gimplify_expr with const ref noreturn paramet (*)
af39be5... d: Fix buffer overflow detected with -defaultlib= and -debu (*)
69f42ef... Daily bump. (*)
1fdbcef... Ada: Fix crash on Unchecked_Union parameter with -gnateV -g (*)
19b33d2... Ada: Fix stack corruption with concatenation and 'Image of (*)
1ad7ee4... d: Fix ICE in ExprVisitor::visit, at d/expr.cc:2224 [PR1234 (*)
1b0d964... d: Fix ICE: in output_constructor_regular_field, at varasm. (*)
e49b8f2... d: Fix ICE: in expand_asm_stmt, at cfgexpand.cc:3445 [PR121 (*)
5e31b24... d: RVO/NRVO not done when returning a copy constructor (*)
c3fa37c... Daily bump. (*)
74eb175... d: Side effects not evaluated for array literals on stack [ (*)
3c7ba15... Update gcc sv.po (*)
0734fef... d: Fix root modules have no file location set [PR122817] (*)
3f5a4b7... c++: non-dep decltype folding of concept-id C<Ts...> [PR123 (*)
1a4b586... c++: leaky uid-sensitive constexpr evaluation [PR122494, PR (*)
15baa18... Daily bump. (*)
7ac25af... Daily bump. (*)
f9dbbff... Daily bump. (*)
8df4ee5... Daily bump. (*)
33a0437... builtins: Only fold abs/absu if it is sane [PR123703] (*)
786def4... openmp: Fix up OpenMP loop parsing in templates [PR123597] (*)
9e109a0... unswitch: Fix up one unguarded fprintf (dump_file, ...) [PR (*)
eaf6cfa... tree-optimization/123741 - fix segfault with BB vect and ma (*)
b543575... tree-optimization/123602 - avoid PRE-inserting abnormal SSA (*)
c4b9eaa... middle-end/123107 - avoid invalid vector folding (*)
e0a00ab... vect: Generalise vect_add_slp_permutation [PR122793] (*)
ba20af7... rs6000: Do not reorder operands for vec_pack_to_short_fp32 (*)
83ba1d0... [APX] i386: Fix illegal broadcast instruction generated by (*)
da3c2f6... x86: Disable tight loop alignment for m_CORE_ATOM (*)
87c0402... Daily bump. (*)
be1c072... arm: fix unrecognized HFmode min/max insns on neon [PR12374 (*)
9237345... libstdc++-v3: Update baseline symbols for ia64-linux (*)
9e2c62a... libstdc++: Fix std::system_category().message(int) on mingw (*)
340b1d3... libstdc++: Fix chrono::parse to read from wide strings [PR1 (*)
47b780b... Daily bump. (*)
973dc10... Ada: Fix visibility issue on generic parent from nested gen (*)
3965c04... Daily bump. (*)
c9f9bfb... c++: Fix member-like friend detection for non-template clas (*)
d549413... c++: Fix ICE with type aliases in inherited CTAD [PR122070] (*)
b327411... [PR122215, IRA]: Add missed test file (*)
4ad723b... Daily bump. (*)
39343db... Update gcc es.po (*)
14da7fd... [PR123092, LRA]: Reprocess insn after equivalence substitut (*)
5a1680b... LoongArch: Fix bug117575. (*)
72f3a41... Daily bump. (*)
bf353ee... Daily bump. (*)
1a248bb... Ada: Fix packed boolean array with Default_Component_Value (*)
8304ea8... Ada: Fix Default_Component_Value aspect wrongly ignored on (*)
e7a9ede... tree: Handle ::operator {new,delete} function templates as (*)
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