https://gcc.gnu.org/g:5ce0e746cb5826b667ee0077ccee3b87422715c1
commit 5ce0e746cb5826b667ee0077ccee3b87422715c1 Author: Peter Bergner <[email protected]> Date: Wed Jan 14 15:12:21 2026 -0600 RISC-V: Enable the ZD constraint only when xmipscbop is enabled [PR123092] The ZD constraint is specific to the mips prefetch instruction. It is currently always enabled, leading to ICEs when xmipscbop is disabled. Solved by only enabling the ZD constraint whenever xmipscbop is enabled. 2026-01-14 Peter Bergner <[email protected]> gcc/ PR target/123092 * config/riscv/constraints.md (ZD): Disable when xmipscbop is disabled. Signed-off-by: Peter Bergner <[email protected]> (cherry picked from commit 58977d739238d927c02f64c6417c887df86a5f55) Diff: --- gcc/config/riscv/constraints.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index dd462c653f3a..f2c2e7214aae 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -333,7 +333,7 @@ (define_address_constraint "ZD" "An address operand that is valid for a mips prefetch instruction" - (match_test "riscv_prefetch_offset_address_p (op, mode)")) + (match_test "TARGET_XMIPSCBOP && riscv_prefetch_offset_address_p (op, mode)")) (define_constraint "Ou07" "A 7-bit unsigned immediate."
