https://gcc.gnu.org/g:b2f71f3307489d6a9f328663a65c88d3a2b9d840
commit b2f71f3307489d6a9f328663a65c88d3a2b9d840 Author: Alexandre Oliva <[email protected]> Date: Sat Jan 31 01:53:12 2026 -0300 testsuite: riscv: pr83403-*.c need common 32bit --param on rv32 Like various other 32-bit CPUs, riscv32 needs to bump the max-completely-peeled-insns param to 300 to meet the expectations. for gcc/testsuite/ChangeLog * gcc.dg/tree-ssa/pr83403-1.c: Bump param on riscv32. * gcc.dg/tree-ssa/pr83403-2.c: Likewise. Diff: --- gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c index 84646b07cab9..f631265edd8e 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O3 -funroll-loops -fdump-tree-lim2-details" } */ /* { dg-additional-options "--param max-completely-peeled-insns=200" { target { s390*-*-* } } } */ -/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { arm*-*-* cris-*-* loongarch32-*-* m68k*-*-* } } } */ +/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { { arm*-*-* cris-*-* loongarch32-*-* m68k*-*-* } || rv32 } } } */ #define TYPE unsigned int diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c index 7c830353ea18..f14b5b4b5fd0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr83403-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O3 -funroll-loops -fdump-tree-lim2-details" } */ /* { dg-additional-options "--param max-completely-peeled-insns=200" { target { s390*-*-* } } } */ -/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { arm*-*-* cris-*-* loongarch32*-*-* m68k*-*-* } } } */ +/* { dg-additional-options "--param max-completely-peeled-insns=300" { target { { arm*-*-* cris-*-* loongarch32*-*-* m68k*-*-* } || rv32 } } } */ #define TYPE int
