https://gcc.gnu.org/g:d931a18247130376de4ecd7543934b5a2d9ae287
commit r16-7299-gd931a18247130376de4ecd7543934b5a2d9ae287 Author: Pan Li <[email protected]> Date: Wed Feb 4 14:00:12 2026 +0800 RISC-V: Adjust testcase asm check for vx-[56]-i[16|8].c Due to middle-end and new param change, adjust the test cases asm check as it cannot be vectorized. PR/target 123916 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c: Adjust the asm check to not. * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c index 2209d565d417..a1de51ba1720 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vrem.vx} } } */ /* { dg-final { scan-assembler {vmax.vx} } } */ /* { dg-final { scan-assembler {vmin.vx} } } */ -/* { dg-final { scan-assembler {vsadd.vx} } } */ -/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c index 26610a6f8397..86f9a29b5f9f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vrem.vx} } } */ /* { dg-final { scan-assembler {vmax.vx} } } */ /* { dg-final { scan-assembler {vmin.vx} } } */ -/* { dg-final { scan-assembler {vsadd.vx} } } */ -/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c index 326971b4bd0a..58730d0a0d4b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c @@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vrem.vx} } } */ /* { dg-final { scan-assembler {vmax.vx} } } */ /* { dg-final { scan-assembler {vmin.vx} } } */ -/* { dg-final { scan-assembler {vsadd.vx} } } */ -/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c index c03f23346c0d..f1eece7266fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c @@ -34,8 +34,8 @@ DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vrem.vx} } } */ /* { dg-final { scan-assembler {vmax.vx} } } */ /* { dg-final { scan-assembler {vmin.vx} } } */ -/* { dg-final { scan-assembler {vsadd.vx} } } */ -/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ /* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2"
