https://gcc.gnu.org/g:4759feb7e92188b65dac815c6b526c4dc4b29d69
commit 4759feb7e92188b65dac815c6b526c4dc4b29d69 Author: Michael Meissner <[email protected]> Date: Fri Feb 6 13:58:05 2026 -0500 PR target/117251: Improve vector nand to vector or fusion See the following post for a complete explanation of what the patches for PR target/117251: * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html This is patch #36 of 45 to generate the 'XXEVAL' instruction on power10 and power11 instead of using the Altivec 'VNAND' instruction feeding into 'VOR'. The 'XXEVAL' instruction can use all 64 vector registers, instead of the 32 registers that traditional Altivec vector instructions use. By allowing all of the vector registers to be used, it reduces the amount of spilling that a large benchmark generated. Currently the following code: vector int a, b, c, d; a = (~ (c & d)) | b; Generates: vnand t,c,d vor a,t,b Now in addition with this patch, if the arguments or result is allocated to a traditional FPR register, the GCC compiler will now generate the following code instead of adding vector move instructions: xxeval a,b,c,239 Since fusion using 2 Altivec instructions is slightly faster than using the 'XXEVAL' instruction we prefer to generate the Altivec instructions if we can. In addition, because 'XXEVAL' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patchs into the trunk? 2026-01-30 Michael Meissner <[email protected]> gcc/ PR target/117251 * config/rs6000/fusion.md: Regenerate. * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to generate vector nand => or fusion if XXEVAL is supported. Diff: --- gcc/config/rs6000/fusion.md | 15 +++++++++------ gcc/config/rs6000/genfusion.pl | 1 + 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index e1d90583f7b3..ff358854ada5 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -2858,20 +2858,23 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vorc (define_insn "*fuse_vandc_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] + [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) + (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) + (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vorc %3,%3,%2 vandc %3,%1,%0\;vorc %3,%3,%2 vandc %3,%1,%0\;vorc %3,%3,%2 + xxeval %x3,%x2,%x1,%x0,244 vandc %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8")]) + (set_attr "length" "8") + (set_attr "prefixed" "*,*,*,yes,*") + (set_attr "isa" "*,*,*,xxeval,*")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vorc diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 3856296e88ec..7f853a2e13e2 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -253,6 +253,7 @@ sub gen_logical_addsubf "vnand_vor" => 239, "vnand_vnand" => 241, "vorc_vnand" => 244, + "vandc_vorc" => 244, "veqv_vnand" => 246, "vnor_vnand" => 247, "vor_vnand" => 248,
