https://gcc.gnu.org/g:26b27d2c956f9896eea85d110b55bbee28c87c0f
commit 26b27d2c956f9896eea85d110b55bbee28c87c0f Author: Michael Meissner <[email protected]> Date: Fri Feb 13 05:01:12 2026 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 211 +++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 195 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index f3c8909e87f2..4d9948741d51 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,24 +1,91 @@ -==================== Branch work237-dmf, patch #100 ==================== +==================== Branch work237-dmf, patch #104 ==================== -Add wD constraint. +Add support for 1,024 bit dense math registers. -This patch adds a new constraint ('wD') that matches the accumulator registers -that overlap with VSX registers 0..31 on power10. Future patches will add the -support for a separate accumulator register class that will be used when the -support for dense math registes is added. +This patch is a prelimianry patch to add the full 1,024 bit dense math register +(DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of the +DMR register. + +This patch only adds the new 1,024 bit register support. It does not add +support for any instructions that need 1,024 bit registers instead of 512 bit +registers. -This patch is the same as the patch posted on November 14th (the follow on -patches in this series will be different). +I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit +registers. The 'wD' constraint added in previous patches is used for these +registers. I added support to do load and store of DMRs via the VSX registers, +since there are no load/store dense math instructions. I added the new keyword +'__dm1024' to create 1,024 bit types that can be loaded into dense math +registers. The patches have been tested on both little and big endian systems. Can I check it into the master branch? -2026-02-12 Michael Meissner <[email protected]> +gcc/ - * config/rs6000/constraints.md (wD): New constraint. - * config/rs6000/mma.md (mma_<acc>): Prepare for alternate accumulator - registers. Use wD constraint instead of 'd' constraint. Use - accumulator_operand instead of fpr_reg_operand. +2026-02-13 Michael Meissner <[email protected]> + + * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec. + (UNSPEC_DM_INSERT512_LOWER): Likewise. + (UNSPEC_DM_EXTRACT512): Likewise. + (UNSPEC_DM_RELOAD_FROM_MEMORY): Likewise. + (UNSPEC_DM_RELOAD_TO_MEMORY): Likewise. + (movtdo): New define_expand and define_insn_and_split to implement 1,024 + bit dense math registers. + (movtdo_insert512_upper): New insn. + (movtdo_insert512_lower): Likewise. + (movtdo_extract512): Likewise. + (reload_tdo_from_memory): Likewise. + (reload_tdo_to_memory): Likewise. + * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add dense math + register support. + (rs6000_init_builtins): Add support for __dm1024 keyword. + * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support + for TDOmode. + (rs6000_function_arg): Likewise. + * config/rs6000/rs6000-modes.def (TDOmode): New mode. + * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add + support for TDOmode. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_hard_regno_mode_ok): Likewise. + (rs6000_modes_tieable_p): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload + hooks for dense math TDO reload mode. + (reg_offset_addressing_ok_p): Add support for TDOmode. + (rs6000_emit_move): Likewise. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_mangle_type): Add mangling for __dm1024 type. + (rs6000_dense_math_register_move_cost): Add support for TDOmode. + (rs6000_split_multireg_move): Likewise. + (rs6000_invalid_conversion): Likewise. + * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode. + (enum rs6000_builtin_type_index): Add dense math register type nodes. + (dm1024_type_node): Likewise. + (ptr_dm1024_type_node): Likewise. + +gcc/testsuite/ + +2026-02-13 Michael Meissner <[email protected]> + + * gcc.target/powerpc/dm-1024bit.c: New test. + * lib/target-supports.exp (check_effective_target_ppc_dm1024_ok): New + target test. + +==================== Branch work237-dmf, patch #103 ==================== + +Add support for dense math registers #3. + +This patch completes support for the dense math registes with 512-bit types. A +future path will add support for 1,024-bit dense registers. + +gcc/ + +2026-02-13 Michael Meissner <[email protected]> + + * config/rs6000/mma.md (mma_<acc>): Add support for dense registers. + Document which instructions are generated by each insn. (mma_<vv>): Likewise. (mma_<avv>): Likewise. (mma_<pv>): Likewise. @@ -26,13 +93,125 @@ it into the master branch? (mma_<vvi4i4i8>): Likewise. (mma_<avvi4i4i8>): Likewise. (mma_<vvi4i4i2>): Likewise. - (mma_<avvi4i4i2>): Likewise. + (mma_<avvi4i4i2): Likewise. (mma_<vvi4i4>): Likewise. (mma_<avvi4i4>): Likewise. - (mma_<pvi4i2): Likewise. + (mma_<pvi4i2>): Likewise. (mma_<apvi4i2>): Likewise. (mma_<vvi4i4i4>): Likewise. - (mma_<avvi4i4i4): Likewise. + (mma_<avvi4i4i4>): Likewise. + * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do + not issue a xxmfacc instruction if we support dense math registers. + * config/rs6000/rs6000-cpu.def (FUTURE_MASKS_SERVER): If -mcpu=future, + turn on -mdense-math. + (POWERPC_MASKS): Mark -mdense-math as being set by -mcpu=<xxx> options. + +==================== Branch work237-dmf, patch #102 ==================== + +Add support for dense math registers #2. + +This patch adds basic support for dense math registers. It includes support for +moving values to/from dense registers. The MMA instructions except for clearing +an accumulator are not yet converted to using dense math registers. + +gcc/ + +2026-02-13 Michael Meissner <[email protected]> + + * config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec. + (movxo): Convert to being a define_expand that can handle both the + original MMA support without dense math registes, and adding dense math + support. + (movxo_nodm): Rename original movxo, and restrict this to when we do not + have dense math registers. + (movxo_dm): New define_insn_and_split for dense math registers. + (mma_xxsetaccz) Convert to being a define_expand that can handle both + the original MMA support without dense math registes, and adding dense + math support. + (mma_xxsetaccz_nodm): Rename original movxo, and restrict this to when + we do not have dense math registers. + (mma_xxsetaccz_dm): New insn for dense math registers. + * config/rs6000/predicates.md (dense_math_operand): New predicate. + (accumulator_operand): Add support for dense math registes. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + __DENSE_MATH__ if dense math registers are used. + * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add dense math + register support. + (enum rs6000_reload_reg_typ): Likewise. + (LAST_RELOAD_REG_CLASS): Likewise. + (reload_reg_map): Likewise. + (rs6000_reg_names): Likewise. + (alt_reg_names): Likewise. + (rs6000_hard_regno_nregs_internal): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_secondary_reload_memory): Likewise. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_secondary_reload_class): Likewise. + (print_operand): Likewise. + (rs6000_dense_math_register_move_cost): New helper function. + (rs6000_register_move_cost): Add dense math register support. + (rs6000_memory_move_cost): Likewise. + (rs6000_compute_pressure_classes): Likewise. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Likewise. + (rs6000_split_multireg_move): Likewise. + * config/rs6000/rs6000.h (UNITS_PER_DM_WORD): New macro. + (FIRST_PSEUDO_REGISTER): Add dense math register support. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (DM_REGNO_P): New macro. + (enum reg_class): Add dense math register support. + (REG_CLASS_NAMES): Likewise. + (REGISTER_NAMES): Likewise. + (ADDITIONAL_REGISTER_NAMES): Likewise. + * config/rs6000/rs6000.md (FIRST_DM_REGNO): New constant. + (LAST_DM_REGNO): Likewise. + * config/rs6000/rs6000.opt (-mdense-math): New option. + + +==================== Branch work237-dmf, patch #101 ==================== + +Add support for dense math registers. + +This patch adds the -mdense-math option for -mcpu=future. The next set of +patches will support for using dense math registers with the MMA instructions. + +gcc/ + +2026-02-13 Michael Meissner <[email protected]> + + * config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define + __DENSE_MATH__ if we have dense math registers. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not + allow -mdense-math unless -mcpu=future is used. + (rs6000_opt_masks): Add -mdense-math support. + * config/rs6000/rs6000.opt (-mdense-math): New option. + * doc/invoke.texi (RS/6000 and PowerPC Options): Add -mdense-math. + +==================== Branch work237-dmf, patch #100 ==================== + +Add wD constraint. + +This patch adds a new constraint ('wD') that matches the accumulator registers +that overlap with VSX registers 0..31 on power10. Future patches will add the +support for a separate accumulator register class that will be used when the +support for dense math registes is added. + +In this patch, I have removed using the wD constriant in mma.md. A later patch +will move to using wA instead of a d constraint. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +2026-02-13 Michael Meissner <[email protected]> + + * config/rs6000/constraints.md (wD): New constraint. * config/rs6000/predicates.md (accumulator_operand): New predicate. * config/rs6000/rs6000.cc (rs6000_debug_reg_global): Print the register class for the 'wD' constraint.
