https://gcc.gnu.org/g:8729a26c800f855e4f0f6fe0a7073dcb51a8573c
commit 8729a26c800f855e4f0f6fe0a7073dcb51a8573c Author: Michael Meissner <[email protected]> Date: Tue May 12 21:10:08 2026 -0400 Add xvrlw testt. This patch adds support for a possible new variant of the vector rotate left instruction that might be added to a future PowerPC. This variant (xvrlw) can use any VSX register instead of requiring only Altivec registers. 2026-05-07 Michael Meissner <[email protected]> gcc/testsuite/ * gcc.target/powerpc/vector-rotate-left.c: New test. Diff: --- .../gcc.target/powerpc/vector-rotate-left.c | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c new file mode 100644 index 000000000000..f9e87ad4bfcf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_future_ok } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Test whether the xvrl (vector word rotate left using VSX registers insead of + Altivec registers is generated. */ + +#include <altivec.h> + +typedef vector unsigned int v4si_t; + +v4si_t +rotl_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x << n) | (x >> (32 - n)); /* xvrlw. */ +} + +v4si_t +rotr_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x >> n) | (x << (32 - n)); /* xvrlw. */ +} + +v4si_t +rotl_v4si_vector (v4si_t x, v4si_t y) +{ + __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */ + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */ +/* { dg-final { scan-assembler-not {\mvrlw\M} } } */
