https://gcc.gnu.org/g:3116e7f7b2138ae94716c76d0ed49d5c7bab6f35
commit 3116e7f7b2138ae94716c76d0ed49d5c7bab6f35 Author: Michael Meissner <[email protected]> Date: Tue May 12 22:25:04 2026 -0400 Revert changes Diff: --- gcc/config/rs6000/altivec.md | 25 ---------------- gcc/config/rs6000/rs6000.opt | 4 --- .../gcc.target/powerpc/vector-rotate-left.c | 34 ---------------------- 3 files changed, 63 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index b7f99e04e7b6..129f56245cd0 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1982,31 +1982,6 @@ } [(set_attr "type" "vecperm")]) -;; -mcpu=future adds a vector rotate left word variant. There is no vector -;; byte/half-word/double-word/quad-word rotate left. This insn occurs before -;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will -;; match the generic insn. -(define_insn "*xvrlw" - [(set (match_operand:V4SI 0 "register_operand" "=v,wa") - (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa") - (match_operand:V4SI 2 "register_operand" "v,wa")))] - "TARGET_XVRLW" - "@ - vrlw %0,%1,%2 - xvrlw %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) - -;; Add a test for the other vector rotate instructions also. -(define_insn "*test_xvrl<VI_char>" - [(set (match_operand:VI2 0 "register_operand" "=v,wa") - (rotate:VI2 (match_operand:VI2 1 "register_operand" "v,wa") - (match_operand:VI2 2 "register_operand" "v,wa")))] - "TARGET_XVRLD && <MODE>mode != V4SImode" - "@ - vrl<VI_char> %0,%1,%2 - xvrl<VI_char> %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) - (define_insn "altivec_vrl<VI_char>" [(set (match_operand:VI2 0 "register_operand" "=v") (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 049fb23d349e..2b6ec5222fc1 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -638,10 +638,6 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. -mxvrld -Target Var(TARGET_XVRLD) Init(0) Save -Generate (do not generate) code that uses the potential XVRL{B,H,D} instructions. - ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c deleted file mode 100644 index f9e87ad4bfcf..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c +++ /dev/null @@ -1,34 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_future_ok } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Test whether the xvrl (vector word rotate left using VSX registers insead of - Altivec registers is generated. */ - -#include <altivec.h> - -typedef vector unsigned int v4si_t; - -v4si_t -rotl_v4si_scalar (v4si_t x, unsigned long n) -{ - __asm__ (" # %x0" : "+f" (x)); - return (x << n) | (x >> (32 - n)); /* xvrlw. */ -} - -v4si_t -rotr_v4si_scalar (v4si_t x, unsigned long n) -{ - __asm__ (" # %x0" : "+f" (x)); - return (x >> n) | (x << (32 - n)); /* xvrlw. */ -} - -v4si_t -rotl_v4si_vector (v4si_t x, v4si_t y) -{ - __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */ - return vec_rl (x, y); -} - -/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */ -/* { dg-final { scan-assembler-not {\mvrlw\M} } } */
