https://gcc.gnu.org/g:5bfb46fc1b95215b412e9213f4f32eb4ee0fb994
commit 5bfb46fc1b95215b412e9213f4f32eb4ee0fb994 Author: Michael Meissner <[email protected]> Date: Fri May 15 21:09:24 2026 -0400 Add paddis support. This patch adds support for the paddis instruction that might be added to a future PowerPC processor. 2026-05-15 Michael Meissner <[email protected]> gcc/ * config/rs6000/constraints.md (eU): New constraint. (eV): Likewise. * config/rs6000/predicates.md (paddis_operand): New predicate. (paddis_paddi_operand): Likewise. (add_cint_operand): Add paddis support. (add_operand): Likewise. * config/rs6000/rs6000.cc (num_insns_constant_gpr): Likewise. (print_operand): Add %B<n> for paddis support. * config/rs6000/rs6000.h (TARGET_PADDIS): New macro. (SIGNED_INTEGER_64BIT_P): Likewise. * config/rs6000/rs6000.md (isa attribute): Add paddis support. (enabled attribute); Likewise. (add<mode>3): Likewise. (adddi3 splitter): New splitter for paddis. (movdi_internal64): Add paddis support. (movdi splitter): New splitter for paddis. * doc/md.texi (PowerPC constraints): Add eU and eV documentation. gcc/testsuite/ * gcc.target/powerpc/prefixed-addis.c: New test. Diff: --- gcc/config/rs6000/constraints.md | 10 +++ gcc/config/rs6000/predicates.md | 75 ++++++++++++++-- gcc/config/rs6000/rs6000.cc | 19 ++++ gcc/config/rs6000/rs6000.h | 10 +++ gcc/config/rs6000/rs6000.md | 104 +++++++++++++++++++--- gcc/doc/md.texi | 6 ++ gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 +++++ 7 files changed, 230 insertions(+), 18 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 0d1cde5bd4de..0169a7b85222 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -222,6 +222,16 @@ "An IEEE 128-bit constant that can be loaded into VSX registers." (match_operand 0 "easy_vector_constant_ieee128")) +(define_constraint "eU" + "@internal integer constant that can be loaded with paddis" + (and (match_code "const_int") + (match_operand 0 "paddis_operand"))) + +(define_constraint "eV" + "@A signed integer constant that paddis and paddi instructions generate." + (and (match_code "const_int") + (match_operand 0 "paddis_paddi_operand"))) + ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 737eafc2bc58..bab7fb103954 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -378,6 +378,65 @@ return SIGNED_INTEGER_34BIT_P (INTVAL (op)); }) +;; Return 1 if op is a 64-bit constant that uses the paddis instruction +(define_predicate "paddis_operand" + (match_code "const_int") +{ + if (!TARGET_PADDIS) + return false; + + if (mode != VOIDmode && mode != DImode) + return false; + + HOST_WIDE_INT value = INTVAL (op); + + if (!SIGNED_INTEGER_64BIT_P (value)) + return false; + + /* If paddi alone can handle the number, don't return true. */ + if (SIGNED_INTEGER_34BIT_P (value)) + return false; + + /* If the bottom 32-bits are non-zero, paddis alone can't handle it. */ + if ((value & HOST_WIDE_INT_C(0xffffffff)) != 0) + return false; + + return true; +}) + +;; Return 1 if op is a 64-bit constant that can be created with a +;; combination of paddi and paddis. Don't generate paddi and paddis if +;; we can do it via addis and rldicl. +(define_predicate "paddis_paddi_operand" + (match_code "const_int") +{ + if (!TARGET_PADDIS) + return false; + + if (mode != VOIDmode && mode != DImode) + return false; + + HOST_WIDE_INT value = INTVAL (op); + + if (!SIGNED_INTEGER_64BIT_P (value)) + return false; + + /* If paddi alone can handle the number, don't return true. */ + if (SIGNED_INTEGER_34BIT_P (value)) + return false; + + /* If we can do the add or generate the constant via addis/rldicl, fail. */ + if (num_insns_constant (op, mode) == 2 + && rs6000_is_valid_and_mask (op, mode)) + return false; + + /* Only return true if we need both paddi and paddis. */ + if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0) + return false; + + return true; +}) + ;; Return 1 if op is a register that is not special. ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where ;; you need to be careful in moving a SFmode to SImode and vice versa due to @@ -568,12 +627,16 @@ (ior (match_operand 0 "zero_constant") (match_operand 0 "gpc_reg_operand"))) -;; Return 1 if op is a constant integer valid for addition with addis, addi. +;; Return 1 if op is a constant integer valid for addition with addis, +;; addi, paddi, or paddis. (define_predicate "add_cint_operand" (and (match_code "const_int") - (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) - + (mode == SImode ? 0x80000000 : 0x80008000)) - < (unsigned HOST_WIDE_INT) 0x100000000ll"))) + (ior (match_test "((unsigned HOST_WIDE_INT) INTVAL (op) + + (mode == SImode ? 0x80000000 : 0x80008000)) + < (unsigned HOST_WIDE_INT) 0x100000000ll") + (match_operand 0 "cint34_operand") + (match_operand 0 "paddis_operand") + (match_operand 0 "paddis_paddi_operand")))) ;; Return 1 if op is a constant integer valid for addition ;; or non-special register. @@ -1122,7 +1185,9 @@ (if_then_else (match_code "const_int") (match_test "satisfies_constraint_I (op) || satisfies_constraint_L (op) - || satisfies_constraint_eI (op)") + || satisfies_constraint_eI (op) + || satisfies_constraint_eU (op) + || satisfies_constraint_eV (op)") (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if the operand is either a non-special register, or 0, or -1. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index f24f5f095bf1..9c40b7e3df5d 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -6166,6 +6166,17 @@ num_insns_constant_gpr (HOST_WIDE_INT value) else if (TARGET_PREFIXED && SIGNED_INTEGER_34BIT_P (value)) return 1; + /* PADDIS support. */ + else if (TARGET_PADDIS && SIGNED_INTEGER_64BIT_P (value)) + { + if ((value & HOST_WIDE_INT_C(0xffffffff)) == 0) + return 1; /* paddis alone. */ + + /* Don't do paddi + paddis if we can do addis and rldicl. */ + if (!rs6000_is_valid_and_mask (GEN_INT (value), DImode)) + return 2; /* paddi + paddis. */ + } + else if (TARGET_POWERPC64) { int num_insns = 0; @@ -14276,6 +14287,14 @@ print_operand (FILE *file, rtx x, int code) fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4); return; + case 'B': + /* Upper 32-bits of a constant. */ + if (!CONST_INT_P (x)) + output_operand_lossage ("Not a constant."); + + fprintf (file, "%" HOST_LONG_FORMAT "d", INTVAL (x) >> 32); + return; + case 'D': /* Like 'J' but get to the GT bit only. */ if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3f50a44cc3d5..f68f431683b3 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -570,6 +570,9 @@ extern int rs6000_vector_align[]; /* Whether we have XVRLW support. */ #define TARGET_XVRLW TARGET_FUTURE +/* Whether we have PADDIS support. */ +#define TARGET_PADDIS (TARGET_FUTURE && TARGET_POWERPC64) + /* Whether the various reciprocal divide/square root estimate instructions exist, and whether we should automatically generate code for the instruction by default. */ @@ -2489,6 +2492,13 @@ typedef struct GTY(()) machine_function #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) +#if HOST_BITS_PER_WIDE_INT > 64 +#define SIGNED_INTEGER_64BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 64) + +#else +#define SIGNED_INTEGER_64BIT_P(VALUE) 1 +#endif + /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra argument that gives a length to validate a range of addresses, to allow for splitting insns into several insns, each of which has an offsettable diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index dfe0402813ce..dd13c3b50697 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -371,7 +371,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10" +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,paddis" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -423,6 +423,11 @@ (and (eq_attr "isa" "p10") (match_test "TARGET_POWER10")) (const_int 1) + + (and (eq_attr "isa" "paddis") + (match_test "TARGET_PADDIS")) + (const_int 1) + ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor @@ -1845,17 +1850,45 @@ }) (define_insn "*add<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") - (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b") - (match_operand:GPR 2 "add_operand" "r,I,L,eI")))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r, r, r, b") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b, b, b, b") + (match_operand:GPR 2 "add_operand" "r,I,L,eI,eU,eV")))] "" "@ add %0,%1,%2 addi %0,%1,%2 addis %0,%1,%v2 - addi %0,%1,%2" + addi %0,%1,%2 + paddis %0,%1,%B2 + #" [(set_attr "type" "add") - (set_attr "isa" "*,*,*,p10")]) + (set_attr "isa" "*,*,*,p10,paddis,paddis") + (set_attr "length" "*,*,*,*,12,24") + (set_attr "prefixed" "*,*,*,*,yes,yes") + (set_attr "maybe_prefixed" "*,*,*,*,no,no")]) + +;; We can't split r0 + large_number due to encoding issues, so use base +;; registers only. + +(define_split + [(set (match_operand:DI 0 "base_reg_operand") + (plus:DI (match_operand:DI 1 "base_reg_operand") + (match_operand:DI 2 "paddis_paddi_operand")))] + "TARGET_PADDIS" + [(set (match_dup 3) + (plus:DI (match_dup 1) + (match_dup 4))) + (set (match_dup 0) + (plus:DI (match_dup 3) + (match_dup 5)))] +{ + HOST_WIDE_INT value = INTVAL (operands[2]); + operands[3] = (can_create_pseudo_p () + ? gen_reg_rtx (DImode) + : operands[0]); + operands[4] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff)); + operands[5] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff)); +}) (define_insn "*addsi3_high" [(set (match_operand:SI 0 "gpc_reg_operand" "=b") @@ -9878,7 +9911,7 @@ DONE; }) -;; GPR store GPR load GPR move +;; GPR store GPR load GPR move GPR paddis GPR paddis+paddi ;; GPR li GPR lis GPR pli GPR # ;; FPR store FPR load FPR move ;; AVX store AVX store AVX load AVX load VSX move @@ -9888,7 +9921,7 @@ ;; VSX->GPR GPR->VSX (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=YZ, r, r, + "=YZ, r, r, r, b, r, r, r, r, m, ^d, ^d, wY, Z, $v, $v, ^wa, @@ -9897,7 +9930,7 @@ r, *h, *h, ?r, ?wa") (match_operand:DI 1 "input_operand" - "r, YZ, r, + "r, YZ, r, eU, eV, I, L, eI, nF, ^d, m, ^d, ^v, $v, wY, Z, ^wa, @@ -9912,6 +9945,8 @@ std%U0%X0 %1,%0 ld%U1%X1 %0,%1 mr %0,%1 + paddis %0,0,%B1 + # li %0,%1 lis %0,%v1 li %0,%1 @@ -9937,7 +9972,7 @@ mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" - "store, load, *, + "store, load, *, *, *, *, *, *, *, fpstore, fpload, fpsimple, fpstore, fpstore, fpload, fpload, veclogical, @@ -9947,7 +9982,7 @@ mfvsr, mtvsr") (set_attr "size" "64") (set_attr "length" - "*, *, *, + "*, *, *, 12, 24, *, *, *, 20, *, *, *, *, *, *, *, *, @@ -9956,14 +9991,32 @@ *, *, *, *, *") (set_attr "isa" - "*, *, *, + "*, *, *, paddis, paddis, *, *, p10, *, *, *, *, p9v, p7v, p9v, p7v, *, p9v, p9v, p7v, *, *, p7v, p7v, *, *, *, - p8v, p8v")]) + p8v, p8v") + (set_attr "prefixed" + "*, *, *, yes, yes, + *, *, *, *, + *, *, *, + *, *, *, *, *, + *, *, *, *, *, + *, *, + *, *, *, + *, *") + (set_attr "maybe_prefixed" + "*, *, *, no, no, + *, *, *, *, + *, *, *, + *, *, *, *, *, + *, *, *, *, *, + *, *, + *, *, *, + *, *")]) ; Some DImode loads are best done as a load of -1 followed by a mask ; instruction. @@ -9981,6 +10034,31 @@ (match_dup 1)))] "") +;; Split a constant that can be generated by a paddis and paddi into 2 +;; instructions. We can't split setting r0 since that would generate: +;; paddis r0,0,upper +;; paddi r0,r0,lower +;; +;; which gives the wrong value. + +(define_split + [(set (match_operand:DI 0 "base_reg_operand") + (match_operand:DI 1 "paddis_paddi_operand"))] + "TARGET_PADDIS" + [(set (match_dup 2) + (match_dup 3)) + (set (match_dup 0) + (plus:DI (match_dup 2) + (match_dup 4)))] +{ + HOST_WIDE_INT value = INTVAL (operands[1]); + operands[2] = (can_create_pseudo_p () + ? gen_reg_rtx (DImode) + : operands[0]); + operands[3] = GEN_INT (value & ~HOST_WIDE_INT_C (0xffffffff)); + operands[4] = GEN_INT (value & HOST_WIDE_INT_C (0xffffffff)); +}) + ;; Split a load of a large constant into the appropriate five-instruction ;; sequence. Handle anything in a constant number of insns. ;; When non-easy constants can go in the TOC, this should use diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 5d6fefdeacae..6fb688da09b7 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3360,6 +3360,12 @@ loaded to a VSX register with one prefixed instruction. An IEEE 128-bit constant that can be loaded into a VSX register with the @code{lxvkq} instruction. +@item eU +A signed integer constant that can be used with the paddis instruction. + +@item eV +A signed integer constant that paddis and paddi instructions generate. + @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c b/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c new file mode 100644 index 000000000000..d08e3675f94c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/prefixed-addis.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_future_ok } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Test whether the xvrl (vector word rotate left using VSX registers insead of + Altivec registers is generated. */ + +#include <stddef.h> + +size_t +prefix_addis_addi (size_t x) +{ + return x + 0x123456789ABCDEUL; /* paddis + paddi. */ +} + +size_t +prefix_addis (size_t x) +{ + return x + 0x12345600000000UL; /* paddis. */ +} + +/* { dg-final { scan-assembler-times {\mpaddis\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
