https://gcc.gnu.org/g:bc94521ad8f375b5e964a8e79c2dccc106d3322d
commit r17-566-gbc94521ad8f375b5e964a8e79c2dccc106d3322d Author: Robin Dapp <[email protected]> Date: Thu Mar 26 16:09:11 2026 +0100 RISC-V: Remove blanket else in riscv_hard_regno_mode_ok. While looking at PR124439 I noticed that we have unreachable code in riscv_hard_regno_mode_ok. Right now we just return false for registers that don't match one of the first four if conditions. This patch just removes the else. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Remove else. Diff: --- gcc/config/riscv/riscv.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0fbc94297ca5..9a0b5c296d91 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -10960,8 +10960,6 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno) || FRM_REG_P (regno)) return true; - else - return false; /* Require same callee-savedness for all registers. */ for (unsigned i = 1; i < nregs; i++)
