https://gcc.gnu.org/g:51a122bf9bf8f01ddfd53fe9e527e93b2ef99ffb
commit r17-912-g51a122bf9bf8f01ddfd53fe9e527e93b2ef99ffb Author: Jeff Law <[email protected]> Date: Thu May 28 11:36:01 2026 -0600 [RISC-V] Fix expected testsuite output after ext-dce changes The recent changes to ext-dce can transform sign extension to zero extension in some cases. As a result tests which previously expected a signed load can now see an unsigned load. Of course on rv32 "lw" loads a full word, so this doesn't show up there. So instead of looking for "lw" we instead look for "(lwu|lw)". This fixes the "regressions" after the ext-dce changes. gcc/testsuite * gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: Adjust expected output. * gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: Likewise. * gcc.target/riscv/amo/a-rvwmo-store-release.c: Likewise. * gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: Likewise. * gcc.target/riscv/amo/a-ztso-store-relaxed.c: Likewise. * gcc.target/riscv/amo/a-ztso-store-release.c: Likewise. * gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c: Likewise. * gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c: Likewise. * gcc.target/riscv/amo/zalasr-rvwmo-store-release.c: Likewise. * gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c: Likewise. * gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c: Likewise. * gcc.target/riscv/amo/zalasr-ztso-store-release.c: Likewise. * gcc.target/riscv/cpymem-64-ooo.c: Likewise. * gcc.target/riscv/cpymem-64.c: Likewise. * gcc.target/riscv/memcpy-nonoverlapping.c: Likewise. * gcc.target/riscv/pr67731.c: Likewise. Diff: --- .../gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c | 2 +- .../gcc.target/riscv/amo/a-rvwmo-store-relaxed.c | 2 +- .../gcc.target/riscv/amo/a-rvwmo-store-release.c | 2 +- .../gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c | 2 +- .../gcc.target/riscv/amo/a-ztso-store-relaxed.c | 2 +- .../gcc.target/riscv/amo/a-ztso-store-release.c | 2 +- .../riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c | 2 +- .../gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c | 2 +- .../gcc.target/riscv/amo/zalasr-rvwmo-store-release.c | 2 +- .../riscv/amo/zalasr-ztso-store-compat-seq-cst.c | 2 +- .../gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c | 2 +- .../gcc.target/riscv/amo/zalasr-ztso-store-release.c | 2 +- gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c | 16 ++++++++-------- gcc/testsuite/gcc.target/riscv/cpymem-64.c | 2 +- gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c | 2 +- gcc/testsuite/gcc.target/riscv/pr67731.c | 3 ++- 16 files changed, 24 insertions(+), 23 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c index b3ec4e1061b1..25d1110829a6 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c +++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c @@ -22,7 +22,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz) /* ** atomic_store_int_seq_cst: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** fence\trw,w ** sw\t[atx][0-9]+,0\(a0\) ** fence\trw,rw diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c index 2f224f993de4..87b0f2fead58 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c +++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c @@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz) /* ** atomic_store_int_relaxed: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c index 6daca225d240..9e75c8d3b4d7 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c +++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c @@ -20,7 +20,7 @@ void atomic_store_long_release (long* bar, long* baz) /* ** atomic_store_int_release: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** fence\trw,w ** sw\t[atx][0-9]+,0\(a0\) ** ret diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c index a1cefbb11097..ff96ab7fa18b 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c +++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c @@ -21,7 +21,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz) /* ** atomic_store_int_seq_cst: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw\t[atx][0-9]+,0\(a0\) ** fence\trw,rw ** ret diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c index 939ad7574625..41e081b768ba 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c +++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c @@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz) /* ** atomic_store_int_relaxed: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c index bb97b8a6d524..f55e4a127957 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c +++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c @@ -19,7 +19,7 @@ void atomic_store_long_release (long* bar, long* baz) /* ** atomic_store_int_release: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c index 7f40d443bd0c..03324eed14fe 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c @@ -20,7 +20,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz) /* ** atomic_store_int_seq_cst: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw.rl\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c index d0127e53baa2..daefe4582ed0 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c @@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz) /* ** atomic_store_int_relaxed: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c index 6174718fe2dd..2b26a24f950b 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c @@ -19,7 +19,7 @@ void atomic_store_long_release (long* bar, long* baz) /* ** atomic_store_int_release: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw.rl\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c index 085f94e5d42f..c53c0f0a424d 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c @@ -20,7 +20,7 @@ void atomic_store_long_seq_cst (long* bar, long* baz) /* ** atomic_store_int_seq_cst: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw.rl\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c index cb68849291b0..c637da07810a 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c @@ -19,7 +19,7 @@ void atomic_store_long_relaxed (long* bar, long* baz) /* ** atomic_store_int_relaxed: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c index b5cc2e967d2a..01c86adf4bd6 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c @@ -19,7 +19,7 @@ void atomic_store_long_release (long* bar, long* baz) /* ** atomic_store_int_release: -** lw\t[atx][0-9]+,0\(a1\) +** (lwu|lw)\t[atx][0-9]+,0\(a1\) ** sw\t[atx][0-9]+,0\(a0\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c b/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c index 147324093cb1..77d38d5e5733 100644 --- a/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c +++ b/gcc/testsuite/gcc.target/riscv/cpymem-64-ooo.c @@ -22,9 +22,9 @@ void copy_aligned_##N (void *to, void *from) \ /* **copy_7: ** ... -** lw\t[at][0-9],0\([at][0-9]\) +** (lwu|lw)\t[at][0-9],0\([at][0-9]\) ** sw\t[at][0-9],0\([at][0-9]\) -** lw\t[at][0-9],3\([at][0-9]\) +** (lwu|lw)\t[at][0-9],3\([at][0-9]\) ** sw\t[at][0-9],3\([at][0-9]\) ** ... */ @@ -33,9 +33,9 @@ COPY_N(7) /* **copy_aligned_7: ** ... -** lw\t[at][0-9],0\([at][0-9]\) +** (lwu|lw)\t[at][0-9],0\([at][0-9]\) ** sw\t[at][0-9],0\([at][0-9]\) -** lw\t[at][0-9],3\([at][0-9]\) +** (lwu|lw)\t[at][0-9],3\([at][0-9]\) ** sw\t[at][0-9],3\([at][0-9]\) ** ... */ @@ -64,7 +64,7 @@ COPY_ALIGNED_N(8) ** ... ** ld\t[at][0-9],0\([at][0-9]\) ** sd\t[at][0-9],0\([at][0-9]\) -** lw\t[at][0-9],7\([at][0-9]\) +** (lwu|lw)\t[at][0-9],7\([at][0-9]\) ** sw\t[at][0-9],7\([at][0-9]\) ** ... */ @@ -75,7 +75,7 @@ COPY_N(11) ** ... ** ld\t[at][0-9],0\([at][0-9]\) ** sd\t[at][0-9],0\([at][0-9]\) -** lw\t[at][0-9],7\([at][0-9]\) +** (lwu|lw)\t[at][0-9],7\([at][0-9]\) ** sw\t[at][0-9],7\([at][0-9]\) ** ... */ @@ -110,7 +110,7 @@ COPY_ALIGNED_N(15) ** ... ** sd\t[at][0-9],16\([at][0-9]\) ** ... -** lw\t[at][0-9],23\([at][0-9]\) +** (lwu|lw)\t[at][0-9],23\([at][0-9]\) ** sw\t[at][0-9],23\([at][0-9]\) ** ... */ @@ -123,7 +123,7 @@ COPY_N(27) ** ... ** sd\t[at][0-9],16\([at][0-9]\) ** ... -** lw\t[at][0-9],23\([at][0-9]\) +** (lwu|lw)\t[at][0-9],23\([at][0-9]\) ** sw\t[at][0-9],23\([at][0-9]\) ** ... */ diff --git a/gcc/testsuite/gcc.target/riscv/cpymem-64.c b/gcc/testsuite/gcc.target/riscv/cpymem-64.c index c91b0154a298..df3a679f1592 100644 --- a/gcc/testsuite/gcc.target/riscv/cpymem-64.c +++ b/gcc/testsuite/gcc.target/riscv/cpymem-64.c @@ -35,7 +35,7 @@ COPY_N(7) /* **copy_aligned_7: ** ... -** lw\t[at][0-9],0\([at][0-9]\) +** (lwu|lw)\t[at][0-9],0\([at][0-9]\) ** sw\t[at][0-9],0\([at][0-9]\) ** ... ** lbu\t[at][0-9],6\([at][0-9]\) diff --git a/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c b/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c index 1c99e13fc269..62f1497adf83 100644 --- a/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c +++ b/gcc/testsuite/gcc.target/riscv/memcpy-nonoverlapping.c @@ -44,7 +44,7 @@ COPY_N(31) /* { dg-final { scan-assembler-times "ld\t" 17 } } */ /* { dg-final { scan-assembler-times "sd\t" 17 } } */ -/* { dg-final { scan-assembler-times "lw\t" 6 } } */ +/* { dg-final { scan-assembler-times "(lwu|lw)\t" 6 } } */ /* { dg-final { scan-assembler-times "sw\t" 6 } } */ /* { dg-final { scan-assembler-times "lhu\t" 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr67731.c b/gcc/testsuite/gcc.target/riscv/pr67731.c index 6f254fc68f5f..4e6f609e24df 100644 --- a/gcc/testsuite/gcc.target/riscv/pr67731.c +++ b/gcc/testsuite/gcc.target/riscv/pr67731.c @@ -20,6 +20,7 @@ _Bool test_01 (S* s) { return s->b | s->c | s->d; } -/* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 } } */ +/* { dg-final { scan-assembler-times {\tlw\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 { target rv32 } } } */ +/* { dg-final { scan-assembler-times {\tlwu\ta0,0\(a0\).*?\n\tandi\ta0,a0,\d+.*?\n\tsnez\ta0,a0.*?\n\tret} 2 { target rv64 } } } */ /* { dg-final { scan-assembler-not {\tor} } } */ /* { dg-final { scan-assembler-not {\tbexti} } } */
