https://gcc.gnu.org/g:548b39f569a308c22fce85a9eedbce93f6f806f8
commit r17-1424-g548b39f569a308c22fce85a9eedbce93f6f806f8 Author: Alfie Richards <[email protected]> Date: Tue Nov 4 11:16:55 2025 +0000 aarch64: Add support for FEAT_SSVE_BitPerm. Adds support for the FEAT_SSVE_BitPerm AArch64 extension. FEAT_SSVE_BitPerm makes the FEAT_SVE2_BitPerm instructions available in streaming mode. gcc/ChangeLog: * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add __ARM_FEATURE_SSVE_BITPERM. * config/aarch64/aarch64-sve-builtins-sve2.def: Make sve-bitperm intrinsics streaming compatible. * config/aarch64/aarch64-sve2.md: Change gating of sve-bitperm instructions. * config/aarch64/aarch64.h (TARGET_SVE_BITPERM): New macro. (TARGET_SVE2_BITPERM): Removed. gcc/testsuite/ChangeLog: * lib/target-supports.exp (exts): Add dg conditions for ssve-bitperm. * g++.target/aarch64/sve/aarch64-ssve.exp: Update test for ssve-bitperm. * gcc.target/aarch64/pragma_cpp_predefs_5.c: Update test. * gcc.target/aarch64/sve2/acle/asm/bdep_u16.c: Update for ssve-bitperm. * gcc.target/aarch64/sve2/acle/asm/bdep_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bdep_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bdep_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bext_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bext_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bext_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bext_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bgrp_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bgrp_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bgrp_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bgrp_u8.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bdep_u16.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bdep_u32.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bdep_u64.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bdep_u8.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bext_u16.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bext_u32.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bext_u64.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bext_u8.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bgrp_u16.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bgrp_u32.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bgrp_u64.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/bgrp_u8.c: Likewise. Diff: --- gcc/config/aarch64/aarch64-c.cc | 5 +- gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 5 +- gcc/config/aarch64/aarch64-sve2.md | 2 +- gcc/config/aarch64/aarch64.h | 10 +-- .../g++.target/aarch64/sve/aarch64-ssve.exp | 7 +- .../gcc.target/aarch64/pragma_cpp_predefs_5.c | 11 ++++ .../gcc.target/aarch64/sme2/acle-asm/bdep_u16.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bdep_u32.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bdep_u64.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bdep_u8.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bext_u16.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bext_u32.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bext_u64.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bext_u8.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bgrp_u16.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bgrp_u32.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bgrp_u64.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sme2/acle-asm/bgrp_u8.c | 74 ++++++++++++++++++++++ .../gcc.target/aarch64/sve2/acle/asm/bdep_u16.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bdep_u32.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bdep_u64.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bdep_u8.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bext_u16.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bext_u32.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bext_u64.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bext_u8.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bgrp_u16.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bgrp_u32.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bgrp_u64.c | 7 +- .../gcc.target/aarch64/sve2/acle/asm/bgrp_u8.c | 7 +- gcc/testsuite/lib/target-supports.exp | 1 + 31 files changed, 990 insertions(+), 23 deletions(-) diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index 2fc28c9babc2..f148bdd39798 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -227,8 +227,11 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) "__ARM_FEATURE_SVE_B16B16", pfile); aarch64_def_or_undef (AARCH64_HAVE_ISA (SVE2), "__ARM_FEATURE_SVE2", pfile); aarch64_def_or_undef (TARGET_SVE2_AES, "__ARM_FEATURE_SVE2_AES", pfile); - aarch64_def_or_undef (TARGET_SVE2_BITPERM, + aarch64_def_or_undef (AARCH64_HAVE_ISA (SVE_BITPERM) + && AARCH64_HAVE_ISA (SVE2), "__ARM_FEATURE_SVE2_BITPERM", pfile); + aarch64_def_or_undef (AARCH64_HAVE_ISA (SSVE_BITPERM), + "__ARM_FEATURE_SSVE_BITPERM", pfile); aarch64_def_or_undef (TARGET_SVE2_SHA3, "__ARM_FEATURE_SVE2_SHA3", pfile); aarch64_def_or_undef (TARGET_SVE2_SM4, "__ARM_FEATURE_SVE2_SM4", pfile); aarch64_def_or_undef (TARGET_SVE2p1, "__ARM_FEATURE_SVE2p1", pfile); diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def index a2ad77106748..1a55de890cf4 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def @@ -205,8 +205,9 @@ DEF_SVE_FUNCTION (svpmullb_pair, binary_opt_n, d_unsigned, none) DEF_SVE_FUNCTION (svpmullt_pair, binary_opt_n, d_unsigned, none) #undef REQUIRED_EXTENSIONS -#define REQUIRED_EXTENSIONS nonstreaming_sve (AARCH64_FL_SVE2 \ - | AARCH64_FL_SVE_BITPERM) +#define REQUIRED_EXTENSIONS streaming_compatible (AARCH64_FL_SVE2 \ + | AARCH64_FL_SVE_BITPERM, \ + AARCH64_FL_SSVE_BITPERM) DEF_SVE_FUNCTION (svbdep, binary_opt_n, all_unsigned, none) DEF_SVE_FUNCTION (svbext, binary_opt_n, all_unsigned, none) DEF_SVE_FUNCTION (svbgrp, binary_opt_n, all_unsigned, none) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index a79d9b6d2496..1d428619c075 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -4398,7 +4398,7 @@ [(match_operand:SVE_FULL_I 1 "register_operand" "w") (match_operand:SVE_FULL_I 2 "register_operand" "w")] SVE2_INT_BITPERM))] - "TARGET_SVE2_BITPERM" + "TARGET_SVE_BITPERM" "<sve_int_op>\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>" [(set_attr "sve_type" "sve_int_bit_perm")] ) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 684673c689d3..538fb4a8e365 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -295,10 +295,12 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED && AARCH64_HAVE_ISA (SVE_AES) \ && TARGET_NON_STREAMING) -/* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */ -#define TARGET_SVE2_BITPERM (AARCH64_HAVE_ISA (SVE2) \ - && AARCH64_HAVE_ISA (SVE_BITPERM) \ - && TARGET_NON_STREAMING) +/* SVE BITPERM instructions, enabled through +sve-bitperm+sve2 for non-streaming + and +ssve-bitperm for streaming. */ +#define TARGET_SVE_BITPERM (AARCH64_HAVE_ISA (SVE_BITPERM) \ + && (AARCH64_HAVE_ISA (SVE2) || TARGET_STREAMING) \ + && (AARCH64_HAVE_ISA (SSVE_BITPERM) \ + || TARGET_NON_STREAMING)) /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */ #define TARGET_SVE2_SHA3 (AARCH64_HAVE_ISA (SVE2) \ diff --git a/gcc/testsuite/g++.target/aarch64/sve/aarch64-ssve.exp b/gcc/testsuite/g++.target/aarch64/sve/aarch64-ssve.exp index ea167eebf0da..eea25abb93b7 100644 --- a/gcc/testsuite/g++.target/aarch64/sve/aarch64-ssve.exp +++ b/gcc/testsuite/g++.target/aarch64/sve/aarch64-ssve.exp @@ -37,7 +37,7 @@ gcc_parallel_test_enable 0 set preamble { #include <arm_sve.h> -#pragma GCC target "+i8mm+f32mm+f64mm+sve2+sve2-bitperm+sve2-sm4+sve2-aes+sve2-sha3+sme+sme2p2" +#pragma GCC target "+i8mm+f32mm+f64mm+sve2+sve2-sm4+sve2-aes+sve2-sha3+sme+sme2p2+ssve-bitperm" extern svbool_t &pred; @@ -146,6 +146,9 @@ set streaming_ok { s8 = svadd_x (pred, s8, s8) s8 = svld1 (pred, s8_ptr) u32 = svcompact (pred, u32) + u8 = svbdep (u8, u8) + u8 = svbext (u8, u8) + u8 = svbgrp (u8, u8) } # This order follows the list in the SME manual. @@ -162,8 +165,6 @@ set nonstreaming_only { u8 = svaese (u8, u8) u8 = svaesimc (u8) u8 = svaesmc (u8) - u8 = svbdep (u8, u8) - u8 = svbext (u8, u8) f32 = svbfmmla (f32, bf16, bf16) f32 = svadda (pred, 1.0f, f32) f32 = svexpa (u32) diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_5.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_5.c index b15d1c953989..bb83ab434b5b 100644 --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_5.c +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_5.c @@ -214,6 +214,17 @@ #endif #pragma GCC pop_options +#pragma GCC push_options +#pragma GCC target "arch=armv8-a+sve2+ssve-bitperm" +#ifndef __ARM_FEATURE_SSVE_BITPERM +#error Foo +#endif + +#ifndef __ARM_FEATURE_SVE2_BITPERM +#error Foo +#endif +#pragma GCC pop_options + int foo (int a) { diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u16.c new file mode 100644 index 000000000000..33f148b35966 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u16.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bdep_u16_tied1: +** bdep z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (bdep_u16_tied1, svuint16_t, + z0 = svbdep_u16 (z0, z1), + z0 = svbdep (z0, z1)) + +/* +** bdep_u16_tied2: +** bdep z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (bdep_u16_tied2, svuint16_t, + z0 = svbdep_u16 (z1, z0), + z0 = svbdep (z1, z0)) + +/* +** bdep_u16_untied: +** bdep z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (bdep_u16_untied, svuint16_t, + z0 = svbdep_u16 (z1, z2), + z0 = svbdep (z1, z2)) + +/* +** bdep_w0_u16_tied1: +** mov (z[0-9]+\.h), w0 +** bdep z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_w0_u16_tied1, svuint16_t, uint16_t, + z0 = svbdep_n_u16 (z0, x0), + z0 = svbdep (z0, x0)) + +/* +** bdep_w0_u16_untied: +** mov (z[0-9]+\.h), w0 +** bdep z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_w0_u16_untied, svuint16_t, uint16_t, + z0 = svbdep_n_u16 (z1, x0), + z0 = svbdep (z1, x0)) + +/* +** bdep_11_u16_tied1: +** mov (z[0-9]+\.h), #11 +** bdep z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u16_tied1, svuint16_t, + z0 = svbdep_n_u16 (z0, 11), + z0 = svbdep (z0, 11)) + +/* +** bdep_11_u16_untied: +** mov (z[0-9]+\.h), #11 +** bdep z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u16_untied, svuint16_t, + z0 = svbdep_n_u16 (z1, 11), + z0 = svbdep (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u32.c new file mode 100644 index 000000000000..69af58b1da02 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u32.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bdep_u32_tied1: +** bdep z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (bdep_u32_tied1, svuint32_t, + z0 = svbdep_u32 (z0, z1), + z0 = svbdep (z0, z1)) + +/* +** bdep_u32_tied2: +** bdep z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (bdep_u32_tied2, svuint32_t, + z0 = svbdep_u32 (z1, z0), + z0 = svbdep (z1, z0)) + +/* +** bdep_u32_untied: +** bdep z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (bdep_u32_untied, svuint32_t, + z0 = svbdep_u32 (z1, z2), + z0 = svbdep (z1, z2)) + +/* +** bdep_w0_u32_tied1: +** mov (z[0-9]+\.s), w0 +** bdep z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_w0_u32_tied1, svuint32_t, uint32_t, + z0 = svbdep_n_u32 (z0, x0), + z0 = svbdep (z0, x0)) + +/* +** bdep_w0_u32_untied: +** mov (z[0-9]+\.s), w0 +** bdep z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_w0_u32_untied, svuint32_t, uint32_t, + z0 = svbdep_n_u32 (z1, x0), + z0 = svbdep (z1, x0)) + +/* +** bdep_11_u32_tied1: +** mov (z[0-9]+\.s), #11 +** bdep z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u32_tied1, svuint32_t, + z0 = svbdep_n_u32 (z0, 11), + z0 = svbdep (z0, 11)) + +/* +** bdep_11_u32_untied: +** mov (z[0-9]+\.s), #11 +** bdep z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u32_untied, svuint32_t, + z0 = svbdep_n_u32 (z1, 11), + z0 = svbdep (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u64.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u64.c new file mode 100644 index 000000000000..7c2dd848e0ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u64.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bdep_u64_tied1: +** bdep z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bdep_u64_tied1, svuint64_t, + z0 = svbdep_u64 (z0, z1), + z0 = svbdep (z0, z1)) + +/* +** bdep_u64_tied2: +** bdep z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bdep_u64_tied2, svuint64_t, + z0 = svbdep_u64 (z1, z0), + z0 = svbdep (z1, z0)) + +/* +** bdep_u64_untied: +** bdep z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bdep_u64_untied, svuint64_t, + z0 = svbdep_u64 (z1, z2), + z0 = svbdep (z1, z2)) + +/* +** bdep_x0_u64_tied1: +** mov (z[0-9]+\.d), x0 +** bdep z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_x0_u64_tied1, svuint64_t, uint64_t, + z0 = svbdep_n_u64 (z0, x0), + z0 = svbdep (z0, x0)) + +/* +** bdep_x0_u64_untied: +** mov (z[0-9]+\.d), x0 +** bdep z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_x0_u64_untied, svuint64_t, uint64_t, + z0 = svbdep_n_u64 (z1, x0), + z0 = svbdep (z1, x0)) + +/* +** bdep_11_u64_tied1: +** mov (z[0-9]+\.d), #11 +** bdep z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u64_tied1, svuint64_t, + z0 = svbdep_n_u64 (z0, 11), + z0 = svbdep (z0, 11)) + +/* +** bdep_11_u64_untied: +** mov (z[0-9]+\.d), #11 +** bdep z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u64_untied, svuint64_t, + z0 = svbdep_n_u64 (z1, 11), + z0 = svbdep (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u8.c new file mode 100644 index 000000000000..e401eb029f95 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bdep_u8.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bdep_u8_tied1: +** bdep z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (bdep_u8_tied1, svuint8_t, + z0 = svbdep_u8 (z0, z1), + z0 = svbdep (z0, z1)) + +/* +** bdep_u8_tied2: +** bdep z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (bdep_u8_tied2, svuint8_t, + z0 = svbdep_u8 (z1, z0), + z0 = svbdep (z1, z0)) + +/* +** bdep_u8_untied: +** bdep z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (bdep_u8_untied, svuint8_t, + z0 = svbdep_u8 (z1, z2), + z0 = svbdep (z1, z2)) + +/* +** bdep_w0_u8_tied1: +** mov (z[0-9]+\.b), w0 +** bdep z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_w0_u8_tied1, svuint8_t, uint8_t, + z0 = svbdep_n_u8 (z0, x0), + z0 = svbdep (z0, x0)) + +/* +** bdep_w0_u8_untied: +** mov (z[0-9]+\.b), w0 +** bdep z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bdep_w0_u8_untied, svuint8_t, uint8_t, + z0 = svbdep_n_u8 (z1, x0), + z0 = svbdep (z1, x0)) + +/* +** bdep_11_u8_tied1: +** mov (z[0-9]+\.b), #11 +** bdep z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u8_tied1, svuint8_t, + z0 = svbdep_n_u8 (z0, 11), + z0 = svbdep (z0, 11)) + +/* +** bdep_11_u8_untied: +** mov (z[0-9]+\.b), #11 +** bdep z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bdep_11_u8_untied, svuint8_t, + z0 = svbdep_n_u8 (z1, 11), + z0 = svbdep (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u16.c new file mode 100644 index 000000000000..05b4121a4283 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u16.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bext_u16_tied1: +** bext z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (bext_u16_tied1, svuint16_t, + z0 = svbext_u16 (z0, z1), + z0 = svbext (z0, z1)) + +/* +** bext_u16_tied2: +** bext z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (bext_u16_tied2, svuint16_t, + z0 = svbext_u16 (z1, z0), + z0 = svbext (z1, z0)) + +/* +** bext_u16_untied: +** bext z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (bext_u16_untied, svuint16_t, + z0 = svbext_u16 (z1, z2), + z0 = svbext (z1, z2)) + +/* +** bext_w0_u16_tied1: +** mov (z[0-9]+\.h), w0 +** bext z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_w0_u16_tied1, svuint16_t, uint16_t, + z0 = svbext_n_u16 (z0, x0), + z0 = svbext (z0, x0)) + +/* +** bext_w0_u16_untied: +** mov (z[0-9]+\.h), w0 +** bext z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_w0_u16_untied, svuint16_t, uint16_t, + z0 = svbext_n_u16 (z1, x0), + z0 = svbext (z1, x0)) + +/* +** bext_11_u16_tied1: +** mov (z[0-9]+\.h), #11 +** bext z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u16_tied1, svuint16_t, + z0 = svbext_n_u16 (z0, 11), + z0 = svbext (z0, 11)) + +/* +** bext_11_u16_untied: +** mov (z[0-9]+\.h), #11 +** bext z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u16_untied, svuint16_t, + z0 = svbext_n_u16 (z1, 11), + z0 = svbext (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u32.c new file mode 100644 index 000000000000..ea340772237a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u32.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bext_u32_tied1: +** bext z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (bext_u32_tied1, svuint32_t, + z0 = svbext_u32 (z0, z1), + z0 = svbext (z0, z1)) + +/* +** bext_u32_tied2: +** bext z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (bext_u32_tied2, svuint32_t, + z0 = svbext_u32 (z1, z0), + z0 = svbext (z1, z0)) + +/* +** bext_u32_untied: +** bext z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (bext_u32_untied, svuint32_t, + z0 = svbext_u32 (z1, z2), + z0 = svbext (z1, z2)) + +/* +** bext_w0_u32_tied1: +** mov (z[0-9]+\.s), w0 +** bext z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_w0_u32_tied1, svuint32_t, uint32_t, + z0 = svbext_n_u32 (z0, x0), + z0 = svbext (z0, x0)) + +/* +** bext_w0_u32_untied: +** mov (z[0-9]+\.s), w0 +** bext z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_w0_u32_untied, svuint32_t, uint32_t, + z0 = svbext_n_u32 (z1, x0), + z0 = svbext (z1, x0)) + +/* +** bext_11_u32_tied1: +** mov (z[0-9]+\.s), #11 +** bext z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u32_tied1, svuint32_t, + z0 = svbext_n_u32 (z0, 11), + z0 = svbext (z0, 11)) + +/* +** bext_11_u32_untied: +** mov (z[0-9]+\.s), #11 +** bext z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u32_untied, svuint32_t, + z0 = svbext_n_u32 (z1, 11), + z0 = svbext (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u64.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u64.c new file mode 100644 index 000000000000..379bfb2e2f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u64.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bext_u64_tied1: +** bext z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bext_u64_tied1, svuint64_t, + z0 = svbext_u64 (z0, z1), + z0 = svbext (z0, z1)) + +/* +** bext_u64_tied2: +** bext z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bext_u64_tied2, svuint64_t, + z0 = svbext_u64 (z1, z0), + z0 = svbext (z1, z0)) + +/* +** bext_u64_untied: +** bext z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bext_u64_untied, svuint64_t, + z0 = svbext_u64 (z1, z2), + z0 = svbext (z1, z2)) + +/* +** bext_x0_u64_tied1: +** mov (z[0-9]+\.d), x0 +** bext z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_x0_u64_tied1, svuint64_t, uint64_t, + z0 = svbext_n_u64 (z0, x0), + z0 = svbext (z0, x0)) + +/* +** bext_x0_u64_untied: +** mov (z[0-9]+\.d), x0 +** bext z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_x0_u64_untied, svuint64_t, uint64_t, + z0 = svbext_n_u64 (z1, x0), + z0 = svbext (z1, x0)) + +/* +** bext_11_u64_tied1: +** mov (z[0-9]+\.d), #11 +** bext z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u64_tied1, svuint64_t, + z0 = svbext_n_u64 (z0, 11), + z0 = svbext (z0, 11)) + +/* +** bext_11_u64_untied: +** mov (z[0-9]+\.d), #11 +** bext z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u64_untied, svuint64_t, + z0 = svbext_n_u64 (z1, 11), + z0 = svbext (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u8.c new file mode 100644 index 000000000000..210f9f70cdb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bext_u8.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bext_u8_tied1: +** bext z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (bext_u8_tied1, svuint8_t, + z0 = svbext_u8 (z0, z1), + z0 = svbext (z0, z1)) + +/* +** bext_u8_tied2: +** bext z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (bext_u8_tied2, svuint8_t, + z0 = svbext_u8 (z1, z0), + z0 = svbext (z1, z0)) + +/* +** bext_u8_untied: +** bext z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (bext_u8_untied, svuint8_t, + z0 = svbext_u8 (z1, z2), + z0 = svbext (z1, z2)) + +/* +** bext_w0_u8_tied1: +** mov (z[0-9]+\.b), w0 +** bext z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_w0_u8_tied1, svuint8_t, uint8_t, + z0 = svbext_n_u8 (z0, x0), + z0 = svbext (z0, x0)) + +/* +** bext_w0_u8_untied: +** mov (z[0-9]+\.b), w0 +** bext z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bext_w0_u8_untied, svuint8_t, uint8_t, + z0 = svbext_n_u8 (z1, x0), + z0 = svbext (z1, x0)) + +/* +** bext_11_u8_tied1: +** mov (z[0-9]+\.b), #11 +** bext z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u8_tied1, svuint8_t, + z0 = svbext_n_u8 (z0, 11), + z0 = svbext (z0, 11)) + +/* +** bext_11_u8_untied: +** mov (z[0-9]+\.b), #11 +** bext z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bext_11_u8_untied, svuint8_t, + z0 = svbext_n_u8 (z1, 11), + z0 = svbext (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u16.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u16.c new file mode 100644 index 000000000000..7ca93671e161 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u16.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bgrp_u16_tied1: +** bgrp z0\.h, z0\.h, z1\.h +** ret +*/ +TEST_UNIFORM_Z (bgrp_u16_tied1, svuint16_t, + z0 = svbgrp_u16 (z0, z1), + z0 = svbgrp (z0, z1)) + +/* +** bgrp_u16_tied2: +** bgrp z0\.h, z1\.h, z0\.h +** ret +*/ +TEST_UNIFORM_Z (bgrp_u16_tied2, svuint16_t, + z0 = svbgrp_u16 (z1, z0), + z0 = svbgrp (z1, z0)) + +/* +** bgrp_u16_untied: +** bgrp z0\.h, z1\.h, z2\.h +** ret +*/ +TEST_UNIFORM_Z (bgrp_u16_untied, svuint16_t, + z0 = svbgrp_u16 (z1, z2), + z0 = svbgrp (z1, z2)) + +/* +** bgrp_w0_u16_tied1: +** mov (z[0-9]+\.h), w0 +** bgrp z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_w0_u16_tied1, svuint16_t, uint16_t, + z0 = svbgrp_n_u16 (z0, x0), + z0 = svbgrp (z0, x0)) + +/* +** bgrp_w0_u16_untied: +** mov (z[0-9]+\.h), w0 +** bgrp z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_w0_u16_untied, svuint16_t, uint16_t, + z0 = svbgrp_n_u16 (z1, x0), + z0 = svbgrp (z1, x0)) + +/* +** bgrp_11_u16_tied1: +** mov (z[0-9]+\.h), #11 +** bgrp z0\.h, z0\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u16_tied1, svuint16_t, + z0 = svbgrp_n_u16 (z0, 11), + z0 = svbgrp (z0, 11)) + +/* +** bgrp_11_u16_untied: +** mov (z[0-9]+\.h), #11 +** bgrp z0\.h, z1\.h, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u16_untied, svuint16_t, + z0 = svbgrp_n_u16 (z1, 11), + z0 = svbgrp (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u32.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u32.c new file mode 100644 index 000000000000..1b8ccf420fb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u32.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bgrp_u32_tied1: +** bgrp z0\.s, z0\.s, z1\.s +** ret +*/ +TEST_UNIFORM_Z (bgrp_u32_tied1, svuint32_t, + z0 = svbgrp_u32 (z0, z1), + z0 = svbgrp (z0, z1)) + +/* +** bgrp_u32_tied2: +** bgrp z0\.s, z1\.s, z0\.s +** ret +*/ +TEST_UNIFORM_Z (bgrp_u32_tied2, svuint32_t, + z0 = svbgrp_u32 (z1, z0), + z0 = svbgrp (z1, z0)) + +/* +** bgrp_u32_untied: +** bgrp z0\.s, z1\.s, z2\.s +** ret +*/ +TEST_UNIFORM_Z (bgrp_u32_untied, svuint32_t, + z0 = svbgrp_u32 (z1, z2), + z0 = svbgrp (z1, z2)) + +/* +** bgrp_w0_u32_tied1: +** mov (z[0-9]+\.s), w0 +** bgrp z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_w0_u32_tied1, svuint32_t, uint32_t, + z0 = svbgrp_n_u32 (z0, x0), + z0 = svbgrp (z0, x0)) + +/* +** bgrp_w0_u32_untied: +** mov (z[0-9]+\.s), w0 +** bgrp z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_w0_u32_untied, svuint32_t, uint32_t, + z0 = svbgrp_n_u32 (z1, x0), + z0 = svbgrp (z1, x0)) + +/* +** bgrp_11_u32_tied1: +** mov (z[0-9]+\.s), #11 +** bgrp z0\.s, z0\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u32_tied1, svuint32_t, + z0 = svbgrp_n_u32 (z0, 11), + z0 = svbgrp (z0, 11)) + +/* +** bgrp_11_u32_untied: +** mov (z[0-9]+\.s), #11 +** bgrp z0\.s, z1\.s, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u32_untied, svuint32_t, + z0 = svbgrp_n_u32 (z1, 11), + z0 = svbgrp (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u64.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u64.c new file mode 100644 index 000000000000..77b37011b248 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u64.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bgrp_u64_tied1: +** bgrp z0\.d, z0\.d, z1\.d +** ret +*/ +TEST_UNIFORM_Z (bgrp_u64_tied1, svuint64_t, + z0 = svbgrp_u64 (z0, z1), + z0 = svbgrp (z0, z1)) + +/* +** bgrp_u64_tied2: +** bgrp z0\.d, z1\.d, z0\.d +** ret +*/ +TEST_UNIFORM_Z (bgrp_u64_tied2, svuint64_t, + z0 = svbgrp_u64 (z1, z0), + z0 = svbgrp (z1, z0)) + +/* +** bgrp_u64_untied: +** bgrp z0\.d, z1\.d, z2\.d +** ret +*/ +TEST_UNIFORM_Z (bgrp_u64_untied, svuint64_t, + z0 = svbgrp_u64 (z1, z2), + z0 = svbgrp (z1, z2)) + +/* +** bgrp_x0_u64_tied1: +** mov (z[0-9]+\.d), x0 +** bgrp z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_x0_u64_tied1, svuint64_t, uint64_t, + z0 = svbgrp_n_u64 (z0, x0), + z0 = svbgrp (z0, x0)) + +/* +** bgrp_x0_u64_untied: +** mov (z[0-9]+\.d), x0 +** bgrp z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_x0_u64_untied, svuint64_t, uint64_t, + z0 = svbgrp_n_u64 (z1, x0), + z0 = svbgrp (z1, x0)) + +/* +** bgrp_11_u64_tied1: +** mov (z[0-9]+\.d), #11 +** bgrp z0\.d, z0\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u64_tied1, svuint64_t, + z0 = svbgrp_n_u64 (z0, 11), + z0 = svbgrp (z0, 11)) + +/* +** bgrp_11_u64_untied: +** mov (z[0-9]+\.d), #11 +** bgrp z0\.d, z1\.d, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u64_untied, svuint64_t, + z0 = svbgrp_n_u64 (z1, 11), + z0 = svbgrp (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u8.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u8.c new file mode 100644 index 000000000000..d4abcd1bbbfa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/bgrp_u8.c @@ -0,0 +1,74 @@ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ + +#include "test_sme2_acle.h" + +#pragma GCC target "+sve2+ssve-bitperm" + +/* +** bgrp_u8_tied1: +** bgrp z0\.b, z0\.b, z1\.b +** ret +*/ +TEST_UNIFORM_Z (bgrp_u8_tied1, svuint8_t, + z0 = svbgrp_u8 (z0, z1), + z0 = svbgrp (z0, z1)) + +/* +** bgrp_u8_tied2: +** bgrp z0\.b, z1\.b, z0\.b +** ret +*/ +TEST_UNIFORM_Z (bgrp_u8_tied2, svuint8_t, + z0 = svbgrp_u8 (z1, z0), + z0 = svbgrp (z1, z0)) + +/* +** bgrp_u8_untied: +** bgrp z0\.b, z1\.b, z2\.b +** ret +*/ +TEST_UNIFORM_Z (bgrp_u8_untied, svuint8_t, + z0 = svbgrp_u8 (z1, z2), + z0 = svbgrp (z1, z2)) + +/* +** bgrp_w0_u8_tied1: +** mov (z[0-9]+\.b), w0 +** bgrp z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_w0_u8_tied1, svuint8_t, uint8_t, + z0 = svbgrp_n_u8 (z0, x0), + z0 = svbgrp (z0, x0)) + +/* +** bgrp_w0_u8_untied: +** mov (z[0-9]+\.b), w0 +** bgrp z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_ZX (bgrp_w0_u8_untied, svuint8_t, uint8_t, + z0 = svbgrp_n_u8 (z1, x0), + z0 = svbgrp (z1, x0)) + +/* +** bgrp_11_u8_tied1: +** mov (z[0-9]+\.b), #11 +** bgrp z0\.b, z0\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u8_tied1, svuint8_t, + z0 = svbgrp_n_u8 (z0, 11), + z0 = svbgrp (z0, 11)) + +/* +** bgrp_11_u8_untied: +** mov (z[0-9]+\.b), #11 +** bgrp z0\.b, z1\.b, \1 +** ret +*/ +TEST_UNIFORM_Z (bgrp_11_u8_untied, svuint8_t, + z0 = svbgrp_n_u8 (z1, 11), + z0 = svbgrp (z1, 11)) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u16.c index c1a4e10614f4..13e9f69ddf45 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u16.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bdep_u16_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u32.c index 4f14cc4c4320..07f3743c5070 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u32.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bdep_u32_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u64.c index 091253ec60b3..f43161436a67 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u64.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bdep_u64_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u8.c index deb1ad27d905..f7b25e89b6c6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bdep_u8.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bdep_u8_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u16.c index 9efa501efa8a..dfba13195e15 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u16.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bext_u16_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u32.c index 18963da5bd3f..d85c6001497a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u32.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bext_u32_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u64.c index 91591f93b887..4f116cda9119 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u64.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bext_u64_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u8.c index 1211587ef41c..ab3b7597360d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bext_u8.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bext_u8_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u16.c index 72868bea7f6f..ea4aff89c77e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u16.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bgrp_u16_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u32.c index c8923816fe41..5c61236d5462 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u32.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bgrp_u32_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u64.c index 86989529fafd..e96ae5c275ab 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u64.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bgrp_u64_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u8.c index 5cd941a7a6ef..55ea7a906e15 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bgrp_u8.c @@ -1,9 +1,14 @@ -/* { dg-skip-if "" { *-*-* } { "-DSTREAMING_COMPATIBLE" } { "" } } */ +/* { dg-do assemble { target aarch64_asm_ssve-bitperm_ok } } */ +/* { dg-do compile { target { ! aarch64_asm_ssve-bitperm_ok } } } */ /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ #include "test_sve_acle.h" +#ifdef STREAMING_COMPATIBLE +#pragma GCC target "+sve2+ssve-bitperm" +#else #pragma GCC target "+sve2-bitperm" +#endif /* ** bgrp_u8_tied1: diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index cba178b937f8..adbaf7d53d07 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -12841,6 +12841,7 @@ set exts { "sme-f8f16" "sme-f8f32" "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "sme2p2" "ssve-fp8dot2" "ssve-fp8dot4" "ssve-fp8fma" "sve-bfscale" "sme-lutv2" + "ssve-bitperm" } foreach { aarch64_ext } $exts {
