https://gcc.gnu.org/g:cb38a9831fa45bb81037798efd36a874b4a6b8d0
commit cb38a9831fa45bb81037798efd36a874b4a6b8d0 Author: Michael Meissner <[email protected]> Date: Thu Jul 16 15:17:51 2026 -0400 PR target/117251: Improve vector fusion #1 See the following post for a complete explanation of what the patches for PR target/117251: * https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686474.html This is patch #1 of 45 to generate the 'XXEVAL' instruction on power10 and power11 instead of using the Altivec 'VAND' instruction feeding into 'VAND'. The 'XXEVAL' instruction can use all 64 vector registers, instead of the 32 registers that traditional Altivec vector instructions use. By allowing all of the vector registers to be used, it reduces the amount of spilling that a large benchmark generated. Currently the following code: vector int a, b, c, d; a = (c & d) & b; Generates: vand t,c,d vand a,t,b Now in addition with this patch, if the arguments or result is allocated to a traditional FPR register, the GCC compiler will now generate the following code instead of adding vector move instructions: xxeval a,b,c,1 Since fusion using 2 Altivec instructions is slightly faster than using the 'XXEVAL' instruction we prefer to generate the Altivec instructions if we can. In addition, because 'XXEVAL' is a prefixed instruction, it possibly might generate an extra NOP instruction to align the 'XXEVAL' instruction. I have tested these patches on both big endian and little endian PowerPC servers, with no regressions. Can I check these patches into the trunk? I have committed all of the patches in my backlog (dense math registers, other -mcpu=future instructions, random bug fixes, support for _Float16 and __bfloat16, and optimizations for vector logical operations on power10/power11) into the IBM vendor branch: vendors/ibm/gcc-17-future 2026-07-16 Michael Meissner <[email protected]> gcc/ PR target/117251 * config/rs6000/fusion.md: Regenerate. * config/rs6000/genfusion.pl (gen_logical_addsubf): Add support to generate vector/vector and/and fusion if XXEVAL is supported. * config/rs6000/predicates.md (vector_fusion_operand): New predicate. * config/rs6000/rs6000.md (isa attribute): Add p10p. (enabled attribute): Add support for XXEVAL support. * config/rs6000/rs6000.h (TARGET_XXEVAL): New macro. Diff: --- gcc/config/rs6000/fusion.md | 15 ++++++----- gcc/config/rs6000/genfusion.pl | 58 ++++++++++++++++++++++++++++++++++++++--- gcc/config/rs6000/predicates.md | 12 +++++++++ gcc/config/rs6000/rs6000.h | 4 +++ gcc/config/rs6000/rs6000.md | 6 ++++- 5 files changed, 84 insertions(+), 11 deletions(-) diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 416017149d6f..68c41114d131 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -1871,20 +1871,23 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vand (define_insn "*fuse_vand_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] + [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") + (and:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") + (match_operand:VM 1 "vector_fusion_operand" "%v,v,v,wa,v")) + (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 + xxeval %x3,%x2,%x1,%x0,1 vand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8")]) + (set_attr "length" "8") + (set_attr "prefixed" "*,*,*,yes,*") + (set_attr "isa" "*,*,*,p10p,*")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vand diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 04e6ab15da6e..3cebfd6d9549 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -211,25 +211,33 @@ sub gen_logical_addsubf $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name, - $fuse_type); - KIND: foreach $kind ('scalar','vector') { + $fuse_type, $xxeval, $c5, $vect_pred, $vect_inner_arg0, $vect_inner_arg1, + $vect_inner_exp, $vect_outer_arg2, $vect_outer_exp); + + my %xxeval_fusions = ( + "vand_vand" => 1, + ); + + KIND: foreach $kind ('scalar','vector') { @outer_ops = @logicals; if ( $kind eq 'vector' ) { $vchr = "v"; $mode = "VM"; $pred = "altivec_register_operand"; + $vect_pred = "vector_fusion_operand"; $constraint = "v"; $fuse_type = "fused_vector"; } else { $vchr = ""; $mode = "GPR"; - $pred = "gpc_reg_operand"; + $vect_pred = $pred = "gpc_reg_operand"; $constraint = "r"; $fuse_type = "fused_arith_logical"; push (@outer_ops, @addsub); push (@outer_ops, ( "rsubf" )); } $c4 = "${constraint},${constraint},${constraint},${constraint}"; + $c5 = "${constraint},${constraint},${constraint},wa,${constraint}"; OUTER: foreach $outer ( @outer_ops ) { $outer_name = "${vchr}${outer}"; $is_subf = ( $outer eq "subf" ); @@ -263,23 +271,33 @@ sub gen_logical_addsubf $bc = ""; if ( $both_commute ) { $bc = "%"; } $inner_arg0 = "(match_operand:${mode} 0 \"${pred}\" \"${c4}\")"; $inner_arg1 = "(match_operand:${mode} 1 \"${pred}\" \"${bc}${c4}\")"; + $vect_inner_arg0 = "(match_operand:${mode} 0 \"${vect_pred}\" \"${c5}\")"; + $vect_inner_arg1 = "(match_operand:${mode} 1 \"${vect_pred}\" \"${bc}${c5}\")"; if ( ($inner_comp & 1) == 1 ) { $inner_arg0 = "(not:${mode} $inner_arg0)"; + $vect_inner_arg0 = "(not:${mode} $vect_inner_arg0)"; } if ( ($inner_comp & 2) == 2 ) { $inner_arg1 = "(not:${mode} $inner_arg1)"; + $vect_inner_arg1 = "(not:${mode} $vect_inner_arg1)"; } $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; + $vect_inner_exp = "(${inner_rtl}:${mode} ${vect_inner_arg0} + ${vect_inner_arg1})"; if ( $inner_inv == 1 ) { $inner_exp = "(not:${mode} $inner_exp)"; + $vect_inner_exp = "(not:${mode} $vect_inner_exp)"; } $outer_arg2 = "(match_operand:${mode} 2 \"${pred}\" \"${c4}\")"; + $vect_outer_arg2 = "(match_operand:${mode} 2 \"${vect_pred}\" \"${c5}\")"; if ( ($outer_comp & 1) == 1 ) { $outer_arg2 = "(not:${mode} $outer_arg2)"; + $vect_outer_arg2 = "(not:${mode} $vect_outer_arg2)"; } if ( ($outer_comp & 2) == 2 ) { $inner_exp = "(not:${mode} $inner_exp)"; + $vect_inner_exp = "(not:${mode} $vect_inner_exp)"; } if ( $is_subf ) { $outer_32 = "%2,%3"; @@ -291,15 +309,23 @@ sub gen_logical_addsubf if ( $is_rsubf == 1 ) { $outer_exp = "(${outer_rtl}:${mode} ${outer_arg2} ${inner_exp})"; + $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_outer_arg2} + ${vect_inner_exp})"; } else { $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; + $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_inner_exp} + ${vect_outer_arg2})"; } if ( $outer_inv == 1 ) { $outer_exp = "(not:${mode} $outer_exp)"; + $vect_outer_exp = "(not:${mode} $vect_outer_exp)"; } - $insn = <<"EOF"; + # See if we can use xxeval on vector fusion + $xxeval = $xxeval_fusions{"${inner_op}_${outer_name}"}; + if (!$xxeval) { + $insn = <<"EOF"; ;; $ftype fusion pattern generated by gen_logical_addsubf ;; $kind $inner_op -> $outer_name @@ -318,6 +344,30 @@ sub gen_logical_addsubf (set_attr "length" "8")]) EOF + } else { + $insn = <<"EOF"; + +;; $ftype fusion pattern generated by gen_logical_addsubf +;; $kind $inner_op -> $outer_name +(define_insn "*fuse_${inner_op}_${outer_name}" + [(set (match_operand:${mode} 3 "${vect_pred}" "=&0,&1,&${constraint},wa,${constraint}") + ${vect_outer_exp}) + (clobber (match_scratch:${mode} 4 "=X,X,X,X,&${constraint}"))] + "(TARGET_P10_FUSION)" + "@ + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} + xxeval %x3,%x2,%x1,%x0,${xxeval} + ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}" + [(set_attr "type" "$fuse_type") + (set_attr "cost" "6") + (set_attr "length" "8") + (set_attr "prefixed" "*,*,*,yes,*") + (set_attr "isa" "*,*,*,p10p,*")]) +EOF + } + print $insn; } } diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 4162c22f8f68..f71f45682412 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -119,6 +119,18 @@ return VSX_REGNO_P (REGNO (op)); }) +;; Return 1 if op is a register that can be used for vector fusion. If XXEVAL +;; is supported, return true for all VSX registers, otherwise the fusion is +;; limited to Altivec registers since the machine only fuses Altivec +;; operations. +(define_predicate "vector_fusion_operand" + (match_operand 0 "register_operand") +{ + return (TARGET_XXEVAL + ? vsx_register_operand (op, mode) + : altivec_register_operand (op, mode)); +}) + ;; Return 1 if op is a vector register that operates on floating point vectors ;; (either altivec or VSX). (define_predicate "vfloat_operand" diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 8235e095bcce..34ae4a149452 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -500,6 +500,10 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) +/* Enable XXEVAL support if we support prefixed instructions and at least + power10. */ +#define TARGET_XXEVAL (TARGET_POWER10 && TARGET_PREFIXED) + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx> options that have not yet been replaced by their OPTION_MASK_<xxx> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4ec3d3da8a99..64043fc20a62 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -369,7 +369,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,future" +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,p10p,future" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -422,6 +422,10 @@ (match_test "TARGET_POWER10")) (const_int 1) + (and (eq_attr "isa" "p10p") + (match_test "TARGET_POWER10 && TARGET_PREFIXED")) + (const_int 1) + (and (eq_attr "isa" "future") (match_test "TARGET_FUTURE")) (const_int 1)
