https://gcc.gnu.org/g:22fe3a35d341d2044c5ced341eec11484b36a18f
commit r17-2525-g22fe3a35d341d2044c5ced341eec11484b36a18f Author: Jiawei <[email protected]> Date: Wed Jun 24 21:44:21 2026 +0800 RISC-V: Add minimal Smctr extension support This adds minimal support for the Smctr[1] (Machine-mode control transfer records) extension, which depends on Zicsr. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv/smctr.adoc gcc/ChangeLog: * config/riscv/riscv-ext.def (smctr): Add new extension. * config/riscv/riscv-ext.opt: Ditto. * doc/riscv-ext.texi: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/smctr-version.c: New test. Diff: --- gcc/config/riscv/riscv-ext.def | 13 +++++++++++++ gcc/config/riscv/riscv-ext.opt | 2 ++ gcc/doc/riscv-ext.texi | 4 ++++ gcc/testsuite/gcc.target/riscv/smctr-version.c | 15 +++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index 4159be567d2a..449f98a29c5e 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -1780,6 +1780,19 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ smctr, + /* UPPERCASE_NAME */ SMCTR, + /* FULL_NAME */ "Machine-mode control transfer records extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zicsr"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ sm, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ smcsrind, /* UPPERCASE_NAME */ SMCSRIND, diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index cfee9551126c..c25a65a1d60d 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -363,6 +363,8 @@ Mask(SMCDELEG) Var(riscv_sm_subext) Mask(SMCNTRPMF) Var(riscv_sm_subext) +Mask(SMCTR) Var(riscv_sm_subext) + Mask(SMCSRIND) Var(riscv_sm_subext) Mask(SMEPMP) Var(riscv_sm_subext) diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index d71ff736bef4..14d8b928daa5 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -526,6 +526,10 @@ @tab 1.0 @tab Cycle and instret privilege mode filtering +@item @samp{smctr} +@tab 1.0 +@tab Machine-mode control transfer records extension + @item @samp{smcsrind} @tab 1.0 @tab Machine-level indirect CSR access diff --git a/gcc/testsuite/gcc.target/riscv/smctr-version.c b/gcc/testsuite/gcc.target/riscv/smctr-version.c new file mode 100644 index 000000000000..8e2852225ac6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/smctr-version.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_smctr1p0 -mabi=lp64" { target { rv64 } } } */ +/* { dg-options "-mriscv-attribute -march=rv32i_smctr1p0 -mabi=ilp32" { target { rv32 } } } */ + +#ifndef __riscv_smctr +#error "Feature macro for 'smctr' not defined" +#endif + +int +foo (void) +{ + return 0; +} + +/* { dg-final { scan-assembler ".attribute arch, .*smctr1p0" } } */
