https://gcc.gnu.org/g:0e73b9c47e0f62eb4df80411f4d45928f80b06cf
commit r15-11535-g0e73b9c47e0f62eb4df80411f4d45928f80b06cf Author: Peter Bergner <[email protected]> Date: Thu Jan 8 20:41:20 2026 -0600 RISC-V: Update tt-ascalon-d8's extension list [PR123492] The Ascalon core implements the full RVA23 profile plus a few other optional extensions. However, the -mcpu=tt-ascalon-d8 option doesn't enable them all. Add the missing extensions. 2026-01-08 Peter Bergner <[email protected]> gcc/ PR target/123492 * config/riscv/riscv-cores.def (RISCV_CORE)<tt-ascalon-d8>: Add missing extensions from the rva23s64 profile and adding zkr. Signed-off-by: Peter Bergner <[email protected]> (cherry picked from commit b8634a0b929cdd6b37275828d6a9fd390b5900c7) Diff: --- gcc/config/riscv/riscv-cores.def | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 2918496bcd06..17aeb3fad841 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -93,11 +93,12 @@ RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadmemidx_xtheadmempair_xtheadsync", "thead-c906") -RISCV_CORE("tt-ascalon-d8", "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_" +RISCV_CORE("tt-ascalon-d8", "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_" "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_" "zifencei_zihintntl_zihintpause_zimop_za64rs_" "zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_" - "zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b", + "zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b_" + "zfhmin_zicntr_zihpm_zkr_zkt_zvfhmin_zvkt", "tt-ascalon-d8") RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_"
