https://gcc.gnu.org/g:5983249d8062eee3820425e1a8a8cbec9a0b7a81
commit r17-3839-g5983249d8062eee3820425e1a8a8cbec9a0b7a81 Author: Pan Li <[email protected]> Date: Tue Sep 1 10:25:42 2026 +0800 RISC-V: Add more test cases for vwmaccus.vx For csrr not asm check when enable overlap enabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-57.c: New test. * gcc.target/riscv/rvv/base/pr112431-58.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../gcc.target/riscv/rvv/base/pr112431-57.c | 62 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr112431-58.c | 62 ++++++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c new file mode 100644 index 000000000000..5c91a7b5f83c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n, uint8_t x) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v0, 1)); + v0 = __riscv_vwmaccus_vx_i16m4_tu (v0, x, v0_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v1, 1)); + v1 = __riscv_vwmaccus_vx_i16m4_tu (v1, x, v1_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v2, 1)); + v2 = __riscv_vwmaccus_vx_i16m4_tu (v2, x, v2_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v3, 1)); + v3 = __riscv_vwmaccus_vx_i16m4_tu (v3, x, v3_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v4, 1)); + v4 = __riscv_vwmaccus_vx_i16m4_tu (v4, x, v4_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v5, 1)); + v5 = __riscv_vwmaccus_vx_i16m4_tu (v5, x, v5_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v6_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v6, 1)); + v6 = __riscv_vwmaccus_vx_i16m4_tu (v6, x, v6_n, 4); + asm volatile("nop" ::: "memory"); + vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100; + vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100; + } +} + +/* The narrowed signed source is the highest-numbered half of the signed + accumulator, thus it overlaps the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c new file mode 100644 index 000000000000..a6da2bc40095 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n, uint16_t x) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint32m4_t v0 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v0_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v0, 1)); + v0 = __riscv_vwmaccus_vx_i32m4_tu (v0, x, v0_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v1 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v1_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v1, 1)); + v1 = __riscv_vwmaccus_vx_i32m4_tu (v1, x, v1_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v2 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v2_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v2, 1)); + v2 = __riscv_vwmaccus_vx_i32m4_tu (v2, x, v2_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v3 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v3_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v3, 1)); + v3 = __riscv_vwmaccus_vx_i32m4_tu (v3, x, v3_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v4 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v4_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v4, 1)); + v4 = __riscv_vwmaccus_vx_i32m4_tu (v4, x, v4_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v5 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v5_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v5, 1)); + v5 = __riscv_vwmaccus_vx_i32m4_tu (v5, x, v5_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v6 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v6_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v6, 1)); + v6 = __riscv_vwmaccus_vx_i32m4_tu (v6, x, v6_n, 4); + asm volatile("nop" ::: "memory"); + vint16m2_t v7_n = __riscv_vle16_v_i16m2 (in, 4);in+=100; + vint32m4_t v7 = __riscv_vwcvt_x_x_v_i32m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse32_v_i32m4 (out, 4, v0, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v1, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v2, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v3, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v4, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v5, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v6, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v7, 4);out+=100; + } +} + +/* The narrowed signed source is the highest-numbered half of the signed + accumulator, thus it overlaps the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */
