https://gcc.gnu.org/g:9c32008587df0c4decf842d9685c5507462bc217
commit r17-3849-g9c32008587df0c4decf842d9685c5507462bc217 Author: Haochen Jiang <[email protected]> Date: Wed Sep 2 16:38:45 2026 +0800 Support BSR0 register For Block Scale Register, although there is only bsr0 for now, we also would like to leave room for future extension for more BSRs and register allocation. Thus, we treat it the similar way as tmm. gcc/ChangeLog: * config/i386/i386.cc (regclass_map): Add BSR_REGS. (debugger_register_map): Add bsr. (debugger64_register_map): Add bsr. (svr_debugger_register_map): Add bsr. (ix86_conditional_register_usage): Enable bsr when ACE exists. (print_reg): Handle bsr. * config/i386/i386.h (FIXED_REGISTERS): Add bsr0. (CALL_USED_REGISTERS): Ditto. (REG_ALLOC_ORDER): Ditto. (HI_REGISTER_NAMES): Add bsr0. * config/i386/i386.md: Add BSR0_REG. * config/i386/predicates.md (bsr0_operand): New. Co-authored-by: Dipesh Sharma <[email protected]> Diff: --- gcc/config/i386/i386.cc | 15 +++++++++++++++ gcc/config/i386/i386.h | 8 ++++++-- gcc/config/i386/i386.md | 3 ++- gcc/config/i386/predicates.md | 5 +++++ 4 files changed, 28 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 9033cfce3b5f..9f2196d54de1 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -181,6 +181,8 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] = GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, /* TMM fake register placeholder */ NO_REGS, + /* Block Scale register */ + NO_REGS, }; /* The "default" register map used in 32bit mode. */ @@ -219,6 +221,8 @@ unsigned int const debugger_register_map[FIRST_PSEUDO_REGISTER] = INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, /* TMM fake register placeholder */ INVALID_REGNUM, + /* Block Scale register */ + INVALID_REGNUM, }; /* The "default" register map used in 64bit mode. */ @@ -251,6 +255,8 @@ unsigned int const debugger64_register_map[FIRST_PSEUDO_REGISTER] = 138, 139, 140, 141, 142, 143, 144, 145, /* tmm fake register placeholder */ IGNORED_DWARF_REGNUM, + /* block scale register */ + IGNORED_DWARF_REGNUM, }; /* Define the register numbers to be used in Dwarf debugging information. @@ -341,6 +347,8 @@ unsigned int const svr4_debugger_register_map[FIRST_PSEUDO_REGISTER] = INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, INVALID_REGNUM, /* TMM fake register placeholder */ INVALID_REGNUM, + /* Block Scale register */ + INVALID_REGNUM, }; /* Define parameter passing and return registers. */ @@ -588,6 +596,12 @@ ix86_conditional_register_usage (void) { CLEAR_HARD_REG_BIT (accessible_reg_set, TMM_REGNUM); } + + /* If ACEV1 is disabled, disable bsr0. */ + if (! TARGET_ACEV1) + { + CLEAR_HARD_REG_BIT (accessible_reg_set, BSR0_REG); + } } /* Canonicalize a comparison from one we don't have to one we do have. */ @@ -14058,6 +14072,7 @@ print_reg (rtx x, int code, FILE *file) putc (msize > 4 && TARGET_64BIT ? 'r' : 'e', file); /* FALLTHRU */ case 2: + case 128: normal: reg = hi_reg_name[regno]; break; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f1bc63ab9815..fc961fb777ca 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1027,6 +1027,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* r24, r25, r26, r27, r28, r29, r30, r31*/ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* tmm*/ \ + 1, \ +/* bsr0*/ \ 1} \ /* 1 for registers not available across function calls. @@ -1070,6 +1072,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* r24, r25, r26, r27, r28, r29, r30, r31*/ \ 1, 1, 1, 1, 1, 1, 1, 1, \ /* tmm*/ \ + 1, \ +/* bsr0*/ \ 1} \ /* Order in which to allocate registers. Each register must be @@ -1087,7 +1091,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ - 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92} + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93} /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order to be rearranged based on a particular function. When using sse math, @@ -2110,7 +2114,7 @@ do { \ "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ - "tmm"} + "tmm", "bsr0"} #define REGISTER_NAMES HI_REGISTER_NAMES diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 6bbb6dbc31ea..69be89a749ac 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -509,7 +509,8 @@ (R30_REG 90) (R31_REG 91) (TMM_REGNUM 92) - (FIRST_PSEUDO_REG 93) + (BSR0_REG 93) + (FIRST_PSEUDO_REG 94) ]) ;; Insn callee abi index. diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 6a2ced036044..289bf807e110 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -97,6 +97,11 @@ (and (match_code "reg") (match_test "MASK_REGNO_P (REGNO (op))"))) +;; Return true if op is the block scale register. +(define_special_predicate "bsr0_operand" + (and (match_code "reg") + (match_test "REGNO (op) == BSR0_REG"))) + ;; Match a DI, SI or HImode register operand. (define_special_predicate "int248_register_operand" (and (match_operand 0 "register_operand")
